11-26-2012 03:13 PM
Is it possible to determine the IOSTANDARD settings either from the device or from the jed file? I archived my ,v files but did not archive the .ucf file. I need to determine the IOSTANDARD used for an old release. Thanks
11-29-2012 08:16 AM
Do you have the ncd and pcf files of the design which was implemented with the ucf?
In such a case you should be able to observe the IOSTANDARD from the PlanAhead tool. Open the ncd and pcf files using the PlanAhead tool and checkf for the particular pin's properties as shown in the figure below.
12-05-2012 02:02 PM
What family of CPLD?
For the 9500XL and XPLA3 family I believe the IOSTANDARD setting was only used for timing analysis and didn't physically enable/disable a particular input/output buffer. (This not the case for CoolRunner-II).
12-18-2012 07:46 AM
Sorry, I got off on another project for a while.
It's cool runner. XC2C128.
Seems like there would be bits at a certain address in the output file, if we just knew what the address was.
12-19-2012 12:41 PM
This should be doable.
Open a webcase and include all information that you have (verilog file, and pinout, and the pins in question).
As long as you clarify that you're not looking to reverse engineer the design (which is not possible) but you are specifically looking for IO configuration settings in the Jedec file, they should be able to help you. If you are vague and just say that you want to reverse engineer the design, they will just say it can't be done.
Post here you run into trouble, I'm watching this thread.