cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
6,374 Views
Registered: ‎09-07-2009

Synthesize error

Jump to solution

Hey ,

 

I  have a problem with  a small pice of my code. I can simulate and it works perfectly but if I want to Synthesize I got following error log:

ERROR:Xst:827 - "//fs6a.iitb.fraunhofer.de/home7/home/gerstn/CL-MUX/CL_SER_1/CL_SER_1/CL_Ser.vhd" line 196: Signal cnt cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

 

This is my code:

 

wee1: process (RSN, data_ready, UCt,WE) 

begin 

if (RSN ='1' ) then
WE <= '0';
cnt <= 0;
elsif (rising_edge (data_ready)) then
 WE <= '1' ;
elsif ( rising_edge (UCt) and WE ='1') then
 cnt <= cnt +1;
 if (cnt = 2) then
 cnt <= 0;
 WE<= '0';
 end if; 
end if;
end process;

 

 --RSN is reset , data_ready is data_Ready, We is write enable,UC is a clock all  are STD LOGIC
--cnt is an integer signal

 

please help me if you can  :) thx

 

Manu

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
7,427 Views
Registered: ‎09-07-2009

Re: Synthesize error

Jump to solution

hey guys,

 

thx for your help. I solved the probem.

 

Manu

View solution in original post

0 Kudos
4 Replies
Highlighted
Teacher
Teacher
6,363 Views
Registered: ‎08-14-2007

Re: Synthesize error

Jump to solution

Hi Manu,

like it's written in your comment lines UC is a Clock (not UCt)

and you can have only one edge sensitive signal in a process.

So:

 

wee1: process (RSN, UC) 

begin 

if (RSN ='1' ) then
WE <= '0';
cnt <= 0;
elsif rising_edge (UC) then
if data_ready = '1' then

  WE <= '1';

end if;

if WE = '1' then

  cnt <= cnt +1;
     if (cnt = 2) then
       cnt <= 0;
       WE<= '0';
    end if; 
end if;
end process;

 

So this will synthesize, I think.

But if it does what you want, I don't know.

 

 edited:

Something else I see is that the reset signal is called RSN.

If the N is n indicator for negative logic you have to change your 

Reset line to:

 if (RSN ='0' ) then...

 

Have a nice synthesis

  Eilert

Message Edited by eilert on 10-21-2009 02:43 PM
0 Kudos
Highlighted
Observer
Observer
6,364 Views
Registered: ‎09-07-2009

Re: Synthesize error

Jump to solution

Hey thx for your help ...but i doesn't do what i want :)  the Problem is that the data_ready Pulse is too short. it's just a quarter of the pulse time of UCt. So the main problem is: How can I create a pulse which is started by the rising edge of the data_ready  and ends with the falling edge uf the UCt. well I have to think about it.

But thanks for your efforts.

 

Greetings

 

Manu

 

 

No with the RSN its all right the N stands ffor NOT but its just to indicate that the PIN outside is low active . Don't worry about that :-)

Message Edited by gerstn on 10-21-2009 05:55 AM
0 Kudos
Highlighted
Professor
Professor
6,353 Views
Registered: ‎08-14-2007

Re: Synthesize error

Jump to solution

If you can use data_ready as an asynchronous set, you wouldn't necessarily need two edge triggered

operations.  You say the pulse is short.  Is it guaranteed to be short enough that it is not still active at

the next falling edge of UCt?  If so you could code:

 

elsif (data_ready) then

 

instead of

 

elsif (rising_edge (data_ready)) then
 

to describe a flip-flop with asynchronous set and reset and falling edge clock.  I'm pretty sure

that will synthesize.

 

Regards,

Gabor

-- Gabor
0 Kudos
Highlighted
Observer
Observer
7,428 Views
Registered: ‎09-07-2009

Re: Synthesize error

Jump to solution

hey guys,

 

thx for your help. I solved the probem.

 

Manu

View solution in original post

0 Kudos