03-24-2015 03:32 PM
We have a situation in which an xc2c128 gets in a hung, non-communicative state. There's an issue with the product design - It uses two diodes as ESD and overvoltage protection on an input: One diode with an anode to ground to limit negative-V spikes, the other with cathode to VCCIO (3.3v) to protect against positive spikes. The input includes a series resistor to limit inrush current. The protected input does -not- connect to a CPLD pin.
VCCIO is generated with an LDO regulator and 1.8v VCC from another LDO supplied from VCCIO. Nice looking power-up and power-down waveforms...
The CPLD hangup occurs, albeit rarely, when circuit power is turned off. The input remains connected, and typically is a 0 to 5v pulse train. As you may have guessed, current from the input passes through the ESD diode and builds up charge on the VCCIO supply capacitors, which in turn causes the VCC LDO output to rise. VCCIO ~= 1V, VCC ~= 0.5v. When power is-re-applied, the CPLD isn't functioning, but the other CMOS and the microcontroller on the board work as expected. If a JTAG cable is connected with the CPLD in this state, any JTAG activity, such as reading back the CPLD via Impact, brings the part back to life.
The long-term solution to the problem will be to replace those clamp diodes with a TVS part that shunts the +V current to ground so no charge gets onto the VCCIO line.
- This does not appear to be CMOS latchup since the input in question does not connect to the CPLD and there is no large current passing through the LDOs with the part in this state.
- VCC drops to a voltage below the reset threshold specified for the part, so I'd think the chip logic would be held in a reset state until VCC rises to spec threshold.
- Both VCCIO and VCC rise and fall monotonically. The spec states that as a requirement and also states there are no sequencing requirements on the voltages. Thus there should be no issue here.
I can prevent the problem by adding load resistance to the LDO outputs. With loads, VCCIO drops to < 0.5v and VCC is close to zero. The spec and app notes appear to be silent on this kind of condition. The question is a point of curiosity. What's going on inside the part?
03-24-2015 03:47 PM
This will not help you, but you are fooling the power on and good logic so that it believes it is working when it is not.
I have no idea why this is so, but the cicuitry used to detect power on and start up is not sophisticated enough to discern that it should be held in reset.
You have already identified how to solve the problem (do not power on the device by this method).
03-25-2015 07:29 AM
Assuming the power source to the LDO has lower resistance to ground when shut off, you could also work around the issue with a diode across the LDO that prevents its output from going above the input power source voltage. This would not burn power all the time the way a load resistor does.