08-22-2013 06:04 AM
I`m new with CPLD and try to divide an external clock by 16. The goal is to supply the divided clock output to a top level signal.(not internal) When I try to do this I can run synthesis, simulation, translation. All is OK. Except the "FIT" process will fail with the following error message:
ERROR:Cpld:1235 - An illegal connection of the clock divider has been detected.
The divided clock output 'C_SCAN_TRIGGER_OUT_OBUF' drives
'C_SCAN_TRIGGER_OUT'. The divided clock output may only drive the clock
input of registers.
My divided clock output is an internal signal "clk4out" But later I will assign clk4out to my external signal but this is not possible.Could anybody help or give an example to supply the divided clock output to a top level signal. thanks in advance:
08-22-2013 06:37 AM
problem solved. according to XAPP378 it is generally not possible:
1. The signal assigned to the CDRST port will automatically be mapped to the CDRST/I/O pin.
2. The output of the clock divider circuit is only available as a clock input to registers within the CPLD.
The clock divider output can not be used in combinational logic or routed off-chip for external use.
3. The clock divider is available on CoolRunner-II 128 macrocell devices and larger.