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Explorer
Explorer
12,937 Views
Registered: ‎05-28-2011

XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hello! I am trying to design a special kind of SR F/F symbolically in ECS. The problem seems to be to enable the fitter to understand that the CP-input is not a static one but actually a low-to-high transition sensitive one (i.e hazard controlled). If the circuit is optimized with CP as a static input it is true that all the inputs to the left of CP can be removed as the optimizer in fact does. I have solved this problem by using an available JK F/F instead but I don't like that solution due to proudness. I want to design my special SR F/F in my own descrete way.

 

I have tried using time constraints in a propagation delay manner but that doesn't help.

 

Can the optimizer be turned off and will that solve the problem?

 

I don't know VHDL or Verilog.

 

Thankful for help!

 

Kind regards, Roger

PS

The optimizer also complains about some possibility of glitches in the Q_inv feedback loop. I can't see that that is a problem with the exception of the well known fact that SR=11 isn't allowed.

fsr_cpl2.PNG
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Accepted Solutions
Instructor
Instructor
10,400 Views
Registered: ‎08-14-2007

Re: Why do I have to tie unused CMOS inputs to GND?

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The unfortunate truth is that CMOS consists of two complementary transistors, each

with a switching threshold based on the opposite power rail.  For 5V CMOS, when

the input is around 2.5V both of these transistors are at least partially conducting.

This provides a path directly from Vcc to ground through the input transistors.  If

you're very unlucky, the input transistors will match well enough that their output

(the center tap of the conducting path) will also sit at about Vcc/2 and cause a similar

issue in the next stage . . . etc.

 

You don't really know if the input leakage current is balanced between the rails

or if it tends toward either Vcc or Ground.  A balanced leakage would tend to pull

the inputs to the threshold region where you draw lots of static power.

 

"Resistors are cheap"

 

-- Gabor

-- Gabor
242 Replies
Teacher eteam00
Teacher
12,918 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Roger,

 

Can you describe in simple text the operation of this special S-R latch?  Or perhaps a truth table might be more straightforward?

 

This will help us to understand what you are trying to accomplish, and possibly suggest an alternate approach for implementation.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
12,910 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi there Bob! Thanks for the fast reply on a saturday night...

 

You have seen the attachment I recon?

 

I have 7 inputs:

D_in : Optional syncronous data input (LD controlled)

LD: Syncronous load enable input (SR must equal 00)

S: Syncronous Set input

R: Syncronous Reset input

CP: Clock input (low-to-high transition)

R_inv: Asyncronous Clear input (active low)

P_inv: Asyncronous Preset input (active low)

and 2 outputs:

Q: F/F output

Q_inv: Inverted F/F output

 

I have attached a truth table and my desperate (but compilable) solution using an already available JK F/F. I could of cource use this and it even gets me the kind of fun feature of SR=11 being allowed (toggling). But I really need my simple descrete version to work. It is too simple to use "IC's" for everything you don't fully understand. At least that is what I think.

 

Kind regards, Roger

fsr_cpl_tt.PNG
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Teacher eteam00
Teacher
12,904 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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I can't write VHDL code to save my life, but here is my Verilog translation of what you have described:

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date:    12:34:21 05/28/2011 
// Design Name: 
// Module Name:    cpld_forum 
//////////////////////////////////////////////////////////////////////////////////
module cpld_forum(
    input Load,			// enable load of D_in
    input SyncSet,		// synchronous set, overrides Load and SyncReset
    input SyncReset,		// synchronous reset, overrides Load
    input D_in,			// D Input
    input Clk,			// clock
    input AsyncSetN,		// async set, active low
    input AsyncResetN,	        // async reset, active low
    output Q,		        // output
    output wire	QN		// output, inverted
    );

reg flop_input;

//synchronous logic terms
always @(*) if (SyncSet) flop_input = 1'b1; // sync set else if (SyncReset) flop_input = 1'b0; // sync reset else if (Load) flop_input = D_in; // load D_in else flop_input = Q; // hold Q
// this is a CPLD flip-flop primitive, with both async set and async reset FDCPE #( .INIT(1'b0) ) // Initial value of register (1'b0 or 1'b1) FDCPE_inst ( // primitive instance named .Q (Q), // FF output .C (Clk), // Clock input .CE (1'b1), // Clock enable input, always enabled .CLR (~AsyncResetN), // Asynchronous clear input .D (flop_input), // synchronous input .PRE (~AsyncSetN) // Asynchronous set input ); assign QN = ~Q; endmodule

It compiles without errors for XPLA3 target.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Instructor
Instructor
12,893 Views
Registered: ‎08-14-2007

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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I think the problem with your initial design has to do with the CP and inverted CP both going

to the inputs of the two three-input NAND gates.  An optimizer will not cleverly infer that

you're using the inverter as a delay element, so it thinks the output of these gates should

always be high.  I believe you could work around this using a KEEP constraint on each

gate or net, but Bob's solution using the actual registers of the CPLD is much better.

For one thing it's not clear that even in a CPLD with macrocells that a single logic

delay as represented by your CP inverter will be guaranteed to propagate through the

following gates and consistently set or reset the output latch.

 

-- Gabor

-- Gabor
Explorer
Explorer
12,889 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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I thank you for your effort! You really must like your job!

 

Here is my solution in a language I can understand, that is basic logical components (I wish I could say gates...).

 

So you don't really know how a clocked Flip/Flop is implemented on gate basis (or in ECS)? Am I to understand that?

 

Anyways, I thank you for your reply. I will not disturb you again. At least not on this topic. Later however when my CPU, realized in your magnificent CPLD, is evolving I might get back to you.

 

Take care!

 

Kind regards, Roger

fsr_cpl_jk.PNG
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Teacher eteam00
Teacher
12,888 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Adding to Gabor's comments...

 

The gate topology in your original post is reminiscent of 1970s TTL latch/FF structure.  7474 D-FFs were implemented in similar fashion because that was the efficient topology for the bipolar technology of the day.  Keep in mind that the gate-level topology was (and is) only a representation of a device (transistor) level circuit implementation.  You cannot infer that a simple interconnection of NAND and NOR gates, as you have described, must work.  You must understand that there is additional work needed at the device level to make clocked functions work reliably.

 

Today's technology, either in ECL/CML or CMOS, implements registers and latches with completely different circuit topology.  A gate-level representation of a typical FF would look very much like two 2:1 MUXes, serially connected.

 

In the case of FPGAs and CPLDs, a successful designer must consider and defer to the structures underlying the various FPGA logic functions.   The logic diagrams and representations are -- for the most part -- oversimplifications of the underlying structures.  In other words, don't try to make a latch or flip-flop using NAND gates in an FPGA or CPLD.  Use the latches and flip-flops which are provided, and let the synthesiser map storage functions to the fundamental storage structures of the target device.

 

What I did was map your function -- not your gate topology -- to the target device.  Nothing more, nothing less.  Implementing your gate topology in FPGA or CPLD structures might have worked reliably, but just as easily might not.

 

Remember the old saying, 'when all you have is a hammer, all your problems look like nails' ?

 

For 74xx 1970s TTL:

When all you have is NAND gates, all your [fill in the blanks]

For FPGAs:

When all you have is FFs and 5-input look-up-tables, all your [fill in the blanks]

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Teacher eteam00
Teacher
12,886 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Roger, this isn't my job.  I don't work for Xilinx.  Nor does Gabor work for Xilinx.

So you don't really know how a clocked Flip/Flop is implemented on gate basis.

I've designed ECL ASICs and FPGAs since the early 1980s, ECL logic systems since the late 1970s, TTL and CMOS logic systems since the early 1980s, and CMOS FPGAs since the late 1980s.  Trust me, I have some understanding of how logic 'gates' are implemented at the silicon (polygon) and device (transistor) level.  I have the grey hair and beard to prove it.

 

What Gabor and I are trying to convey to you is that the gate-level designs you have developed are based on 'gates' which do not exist in today's FPGAs and CPLDs. The 'gates' you see in the design docs and user guides are representations of  look-up-tables configured to mimic the represented gate

 

To faithfully realise your designs, you will need to resort to honest-to-goodness 'discrete' SSI logic or 1970s era TTL foundry libraries.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Explorer
Explorer
12,882 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Gabor!

 

Thank you for your input to my "problem". But how is a clocked F/F implemented in the CPLD then? It has to use a circuitry somewhat like mine with a hazard (due to propagation delay and shown connection) generated glitch, clocking in data at optional clock pulse transition.

 

Kind regards, Roger

PS

Sending you a fun home made picture of a 74HC00 glitch.

HCMOS-spike.png
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Explorer
Explorer
12,876 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Bob, I can't help but laughing at your comments and my ignorance! I will KODO you asap!

 

Once again, thank you for your reply and interest in my obsolete "problem"! And I am very impressed of your working background!

 

Take care!

 

Kind regards, Roger

PS Me, I am just repairing CPU-based (and CPLD-armed) circuit boards all day long. It is actually quite fun because the failures are different all the time and you just have to find them which is the only engineering part of my work. And I miss designing stuff. So now I have decided to try designing a CPU in CPLD technology (instead of wireing a square-meter of descrete gates...).

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Teacher eteam00
Teacher
10,769 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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But how is a clocked F/F implemented in the CPLD then?

CPLDs are CMOS devices.  To a first approximation, this is a good representation of a CMOS FF circuit.  At a more abstract level, it's two 2:1 MUXes, back to back.  First MUX is the master latch, the second MUX is the slave latch.  Together, it's an edge-triggered FF.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Explorer
Explorer
10,769 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Gabor!

 

How do I set a KEEP constraint? Still interested in my obsolete design as you can see...

 

Kind regards, Roger

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Teacher eteam00
Teacher
10,767 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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I have decided to try designing a CPU in CPLD technology

Have you read about PicoBlaze?  There is a version designed for CoolRunner II CPLDs.

Start here.  You'll need to register and enter your secure sign-in.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Instructor
Instructor
10,758 Views
Registered: ‎08-14-2007

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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rogerk8 wrote:

Hi Gabor!

 

How do I set a KEEP constraint? Still interested in my obsolete design as you can see...

 

Kind regards, Roger


 

Hi Roger,

 

You'll need to check out the Constraints guide which is available from the Help menu

of the ISE project navigator.  I don't generally design with schematics these days,

having opted to use Verilog instead.  So the actual method of applying the constraint

will be different since it is in the source and therefore depends on the design entry

method.  I believe that for a CPLD a KEEP constraint on a net, like the output of

your inverter feeding the two 3-input NAND gates, should force the inverter to use its

own macrocell rather than being mashed together into a single macrocell with

the NAND gates.  It might make sense for you to look through the XPLA3 family

data sheet to see how the macrocells are implemented.  This can give you an idea

of how your "gates" end up in the final design.

 

I seem to remember a very elegant D flip-flop block diagram in the original TTL data

book from Texas Instruments (yes I'm also grey on top like Bob and have been

designing since the days before programmable logic using pencil on vellum) that

used 6 3-input NAND gates to form one 7474 type D flip-flop with asynchronous

set and clear.  It's not obvious that even those flip-flops actually used the circuit

shown in the block diagram.  Other manufacturers show representations of

the D flip-flop using transfer gates (like a 74125 tristate buffer), which is probably

closer to the CMOS implementations.  Nowadays, most semiconductor manufacturers

assume you know the behavior of a D flip-flop and don't actually show the

construction in their data sheets.  In some cases the information is proprietary,

but in all cases the idea is that you only need to know the behavioral model

in order to use the device.  I suspect that Xilinx will not divulge the actual

structure of their flip-flops.  Rest assured, however that they are designed to

work very well in terms of setup and hold timing, metastability resistance,

and propagation delay.  Any attempt to use the combinatorial logic elements

in a CPLD or FPGA cannot come close to the performance of these flip-flops,

and if you're not careful (as you've already found out) results in something

that doesn't work at all.  I'm not saying that it isn't interesting to build sequential

logic from gates.  I've done it myself when I was using PAL16L8's and needed

a single flip-flop with unremarkable characteristics.  I just don't see how designing

sequential logic from gates will help you in your endeavor to make a CPU.

You're better off learning how to best use the resources available in your

CPLD.  Using multiple macrocells to build a simple flip-flop wastes a lot

of these resources.  In my early design days I would always look through the

part catalogs to see which MSI TTL devices could implement a significant

portion of my design.  This didn't mean that I couldn't design the function from

gates.  It's just good design practice to minimise the number of parts in

a system.  For programmable logic, this still holds true in that it's beneficial

to fit your design in the fewest chip resources.  This allows you to use the

smallest, cheapest part to get the design done.  And implementing a design

in a way that minimises on-chip resources holds as much fun and challenge

as learning how to build it from simple gates.

 

I wish you good luck in your design endeavors.  Hopefully the challenges of

designing with programmable components (and not against them or in spite

of them) will hold your interest and help you to succeed.

 

Regards,

Gabor

-- Gabor
Teacher eteam00
Teacher
10,754 Views
Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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I believe that for a CPLD a KEEP constraint on a net, like the output of your inverter feeding the two 3-input NAND gates, should force the inverter to use its own macrocell rather than being mashed together into a single macrocell with the NAND gates.

From the ISE Language Templates menu, under UCF > CPLD > Optimization > KEEP:

# KEEP prevents a net from being optimized forward into a MC Pterm.
 NET mysignal KEEP;
# Families: All CPLD.
# Applies to any signal except input pads.

Here's an alternative to a 'KEEP' constraint:  Make the intermediate term an output signal.  Might work!

yes I'm also grey on top like Bob and have been designing since the days before programmable logic using pencil on vellum

Did I ever tell you about the licensing fees for stone tablets and chisels?  That's when design tools really were tools.  The design tools were supplied by Apollo -- and we're not talking about the workstation outfit, we're talking about the Mt. Olympus Apollo.  Ah yes, the days of my youth...

 

I, too, abused PLDs at one point in my long and ?? career.  My favourite MSI 'can do most anything' devices were 8:1 decoder and dual 4:1 multiplexer.  74138 and 74153, I believe.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Explorer
Explorer
10,737 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Gabor!

 

I thank you for your essay. It was very fun and interesting to read. I recognize that I don't know much about modern CPLD programming. I don't even know what a macrocell is, it's implementation or it's capacity. I am just a stupid beginner who has a crazy but fun idea. The reason for me being stubborn about the obsolete FF design is because I already have my CPU designed on paper/Wikibooks using nothing but gates. And I just want to implement it in my target CPLD. It is however not said that I must implement it that way. In view of what both you and Bob have said it seems like a good idea to make fully use of the device capacity instead of stubbornly continue my journey in the technology of the 70's.

 

Just read about macrocells on Wikipedia. There was not much said but I think I am a little bit wiser now because the definition of a macrocell seems to be a "prefabricated array of higher-level logic functions". But I kind of knew that.

 

Next small step is to design a byte-register using my upgraded SR-FF (using predefined JK-FF's). I know there are fredefined registers too but I kind of suspect that they won't perform my exact wishes. A bigger problem here is actually how to schematically design my upgraded FF at low-level instead of top-level. But I will make use of the ISE Help for this.

 

Thanks again for the effort and interest in helping me!

 

Kind regards, Roger
PS
If you like you may view my crazy design at http://sv.wikibooks.org/wiki/CPU_design . It is unfortunatelly written in swedish but you might appreciate some pictures. Furthermore, the book is quite messy and not that accurate (I recommend you to jump to part2 i.e del2).

 

CPU 1.2 will preliminary not have neither a multiplier nor a divider. This is partially because I don't know how to implement them, partially that I've played with the thought of shifting left as multiplying and shifting right as dividing (by multiples of two which may or may not be possible to approximate in SW).

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Just read about macrocells on Wikipedia. There was not much said but I think I am a little bit wiser now because the definition of a macrocell seems to be a "prefabricated array of higher-level logic functions". But I kind of knew that.

Macrocell specifics vary from one family of CPLD to another. For the XPLA3 family, DS012.pdf, Figure 5.

I am just a stupid beginner who has a crazy but fun idea. The reason for me being stubborn about the obsolete FF design is because I already have my CPU designed on paper/Wikibooks using nothing but gates. And I just want to implement it in my target CPLD.

Have you read Don Quixote lately?  :)

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Explorer
Explorer
10,720 Views
Registered: ‎05-28-2011

Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Bob!

 

Once again I thank you for your kind and funny reply. I laughed aload. I have much to learn! But I read the macrocell part of the link you thankfully supplied and I actually got somewhat more wiser. But I don't know how to use the information. Maybe it would be better if I actually read Don Quixote :-)

 

Anyways, I understand what you mean. But I am a stubborn man as you might have noticed. I am not even sure that I will use the upgraded version of my FF. I might want to implement it EXACTLY as I have planned (using the KEEP constraint). But I don't know. Who is actually interested in HOW you implement stuff? Isn't the goal the most interesting part? Not the way you got there, I mean. For me it is the way you got there, but for others? No, I think I will make use of the predefined logic functions as much as I can and afterwards my pride will have to shift from the actual implementation to the result.

 

It is fun to chat with you experts and I am moved about the interest and effort you put into my problem. It inspires me! And I know that my project is obsolete in many ways. But I really don't care. I will build my CPU in one way or the other. And while it for certain won't be able to compete with Intel, I really don't care. My far away goal is to build a computer from scratch. And something like MS-DOS to superwise it. Rediculous, don't you think?

 

Kind regards, Roger Knopp

 

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Explorer
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Bob!

 

Now I have managed to schematically design an 8-bit register with my own upgraded symbol of a SR-FF. It was actually kind of hard to get ECS to involve my symbol but finally I managed. Don't ask me how but this fact made me very happy. I was using the ECS help but understood almost nothing :-)

 

It seems like I'm kind of getting there but still it's a long way to go. I'm attaching the schematics.

 

Take care!

 

Kind regards, Roger Knopp

PS

I read your links about CMOS circuits. It was very interesting but I knew the basic parts, that is how a CMOS inverter is implemented, but when it came to transmission gate FF's I kind of lost the trail.

sr_ff.PNG
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Teacher eteam00
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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but when it came to transmission gate FF's I kind of lost the trail.

That's OK, Xilinx takes care of the details for you, but only if you let them.

 

-- Bob Elkind

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
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Instructor
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Transmission gates are simple enough.  Think of them as On/Off switches controlled by a logic input.

In the diagram from Bob's link, they look more complex because the diagram shows a bit more of

the switch structure, in that its gate input consists of two complementary gates.  They are always

driven to opposite rails - thus the inverters between the two drivers.  When the top input is low

and the bottom input is high then the switch conducts.  When the bottom input is low and the top input

is high the switch is off.  The switch itself is a complementary (the "C" in CMOS) pair of MOS-FETs.  The

two FETs are wired in parallel as pass transistors so the top input of the transmission gate represents

the PFET gate and the bottom input is the NFET gate.  Source and drain are left and right terminals

and for these structures are relatively symmetrical so it doesn't really matter which side is source or

drain.  Each of the two FETs conducts best when the channel voltage going through the switch is

at the opposite rail from its gate, so you get fairly good conduction over the whole voltage range

from ground to Vdd.

 

As you know, a flip-flop or latch requires feedback to hold its current state.  The simplest gated latch

in CMOS can be a transmission gate in the feedback path of a non-inverting buffer.  When the switch

is on, the buffer feeds its own input and thus holds its state.  Another transmission gate on the input

side of this structure turns off to prevent the feedback from driving the latch's input when the feedback

transmission gate is turned on.

 

Regards,

Gabor

-- Gabor
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Bob!

 

I am sorry for disturbing you again. You have helped me more than enough. But I really love Xilinx and their fantastic products. I can hardly understand that there's actually a way to design a CPU just by programming (and not tedious hardwiring). What fantastic evolution that is! It is for sure amazing and I am very happy about this opportunity.

 

I am progressing in some small steps. Now, I have created an 8-bit register symbol using my upgraded FF and I am kind of proud about it which is why I send you this copy.

 

I am perhaps too keen of telling you the way my project proceeds but it seems like you're not that uninterested. On the other hand, I just wish to continue designing and don't really need to tell you about my progress. But it is very fun doing so!

 

Take care!

 

KInd regards, Roger Knopp

PS

What is the frequency limit? I for sure don't need no 3GHz processor but it would be fun to know.

 

 

CPU_Register.PNG
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Teacher eteam00
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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I have created an 8-bit register symbol using my upgraded FF and I am kind of proud about it which is why I send you this copy.

Thank you.  It looks like you are well on your way

What is the frequency limit? I for sure don't need no 3GHz processor but it would be fun to know.

The ISE tools will tell you the expected operating frequency range of your design.  Also, there are many timing specification details in the device datasheet. The performance characteristics will vary with device and speed grade.  If you are using the XCR3128XL, the datasheet is here.  The XC3128XL is spec'd for up to 175MHz "Maximum system frequency", for the fastest speed grade.  Even with the slowest speed grade, you should have no trouble running around 90MHz or so, if you use the CPLD's 'native' flip-flops.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Gabor!

 

I kind of understand nothing of what you've just said. I am just thankful of your reply. Actually, I have never heard of this approach in designing FF's. It is totally forain to me. I however know that it is possible to use Complemtary MOS for analogue switches but I kind of thought that that was their limit. And when I heard Bob talking about FF's realized in CMOS technology I was lost.

 

A beginners question, how come my SR-FF has to use two macrocells? I happen to see this when I was trying to compile my design. It seems like it depends on my stubborn use of two complementary outputs. And this seems like a waste of density (is it called that?).

 

Than you for your detailed and nice reply!

 

Kind regards, Roger Knopp

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Teacher eteam00
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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A beginners question, how come my SR-FF has to use two macrocells?

Think of each macrocell as a single AND-OR gate with optional flip-flop on the output.  This is an oversimplification, but it's a reasonable approximation for your application.

 

Any AND-OR term which is fed back to the input requires (consumes) a macrocell.  I'm surprised your SR-FF consumes only two macrocells.  I suspect your SR-FF has been 'optimised' (logic minimised) to the point of not functioning as you intend.

 

It's not too late to simply use the SR-FF capability which is intrinsic to the CPLD.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Bob!

 

Jesus, that is good! I could almost design a Pentium. Just kidding, but 100MHz is much. And It is fun that that speed is available, but I don't expect that. I just want it to work. And if it's 1MHz I really don't care. But it is fun to know the CPLD potential. Thank You!

 

Kind regards, Roger Knopp

PS

This project is, due to you kind and skilled experts, getting more fun by the hour.

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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Hi Bob!

 

I have a few questions. Maybe I should have started a new subject but for simplicity I will just continue here.

 

1) What are the separate CLK-inputs used for? Are they heavily buffered or what? I have created an CP-signal which is used everywhere within the CPU and perhaps just connecting it to a pin won't suffice?

 

2) ECS complains (Check Schematic) about me not being able to connect a three-state buffer's output to another three-state buffer's output. But isn't this the hole point of using a three-state buffer (with output enable)? I need to create a bus and will have several modules hanging on the bus. ECS however says that it will use "wired-or" instead. Perhaps this isn't a problem but just a warning but I think it is strange that it complains.

 

3) I have designed my modules with special consideration taking to presetting the counters and registers using a global asyncronous negative pulse. I have however seen somehwere in the toturial that FF's at POR (Power On Reset) can be predetermined. Am I designing in a wrong way or can I continue? I just need to generate an external negative glitch which is quite easy to do (but this goes to several gates too).

 

4) What are all the supply pins used for? Minimizing inductance and resistive losses or what? Because I imagine that they are all connected to the same point. DC-wice, that is. So if I will run my CPU at a low speed, I need only to connect to a single pair of supply?

 

Take care!

 

Kind Regards, Roger Knopp

PS

Attaching a newly designed part of my CPU. It is the one and only Accumulator. It is by the way quite fun to actually use the autorouter :-)

CPU_AC.PNG
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Teacher eteam00
Teacher
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home-brew CPU on a CPLD

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I have a few questions. Maybe I should have started a new subject but for simplicity I will just continue here.

 

No problem from my end.

 

1)  If your design uses a clock (and it does), you should use one of the clock input pins.  I'm just guessing (I'm an FPGA weenie, not a CPLD weenie) that there is specially optimised buffering and interconnect available for clock input pins, with the result being minimised skew and minimised setup and hold times.  I know you don't like to do things the conventional way, but maybe it's worth using a clock input pin for your clock input signal, even though Xilinx says it's a good idea.  :)

 

2)  3-state buffers allow you to use a single pin for both input and output.  There is no interconnect on the CPLD for wire-ORing two 3-state "outputs" internally, but there are two simple and reasonable workarounds.

 

a)  Connect the two outputs to two package pins, and connect them together externally (on the circuit board).

 

b)  Mux the two "D" logic terms internally (in logic) to a single output signal, and OR the two output enables to a single output enable, and use a single 3-state output buffer which combines the two.

 

3)  If initial state at power-on can be defined in your code, then there is no need for an external async reset input.  This also makes it simple to generate your own internal single-cycle synchronous (or async, if you prefer) reset pulse without using an input pin or generating a weird "glitch".

 

4)  Yes, multiple GND and supply pins reduce supply inductance, which in turn improves on-chip GND/supply noise.  Noise is induced by supply current transients (dI/dt) passed through inductors (i.e. package pins).  Current transients are generated by signal switching.  Such switching occurs on clock edges, regardless of clock frequency.  Clock frequency affects the frequency of the current transients (or spikes), but not the amplitude of the transients.  So it is a good idea to connect all supply and GND pins, even for low-frequency designs.  Dare to be conventional!

 

Does this all make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Instructor
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Re: XPLA3 XCR3128XL, SR-Flip/Flop Design Problem

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Roger,

 

  I've got a bit of experience in CPLD's going back to the Mach110 and Mach210 series, which

looked a lot like a few PALs connected together in one package.  I suggest you open the XPLA3

family data sheet (not the one for your specific device) and look through the section on the

architecture.  This will geve you a better feel for how your schematic or HDL gates get translated

into the actual gate structure of the device.

 

1) In the older PAL and GAL type devices, all of the flip-flops would have their clock tied directly

to the clock input pin of the device.  Most modern CPLDs allow you to use a product term

output (output of a wide AND gate shown horizontally in figure 2 on page three of the

above data sheet).  Generally the setup/hold requirements of a flip-flop using the global

clock input are easier to meet than for a flip-flop using a product term clock.  Note that

general I/O pins have no direct routing to the clock input of a flip-flop, so you'd use a

product term even though the AND gate only uses one input in that case.

 

Try not to get overwhelmed by the strange look of the array diagrams.  In figure 2, for example

the vertical lines represent internal signals in the macrocell array.  The horizontal lines

represent possible connections to each AND gate.  They are physically buses, with a wire

to the N-input AND gate for each of the N vertical lines crossing it in the array.  For each

intersection there is a switch (literally a fuse in the original PAL devices) that either connects

the signal on that vertical line to an input of the AND gate or ties that AND gate input high.

So basically each "product term" represents the AND of any of the internal signals in the

array.  The vertical array usually consists of all of the inputs to one of the macrocell arrays

and the inversion of all of those inputs as well.  So a macrocell array with 18 inputs would

have 36 vertical lines (minimum - for some architectures the vertical array also contains

feedback nets from the OR gate outputs).

 

Since you seem to like working with logic gates, perhaps you'll find it an enjoyable

exercise to design logic that uses the available AND/OR structure to its maximum

effectiveness.  The XPLA architecture for example allows you to re-use the same

AND gates (product terms) due to the OR array on the outputs of these gates.  So

structuring multiple signals to have common AND terms can give you more effective

gates from the same array.

 

2) Bob explained this pretty well.  Essentially tri-states are for external use only.

 

3) I think it is a good design practice to have a global reset in a design.  For one thing,

it makes the design easier to simulate.  In FPGA's the configuration process initializes

every flip-flop and memory cell to a known initial value.  Not all CPLD's work like this,

so you need to review the data sheet.  If you find you don't need to reset every flip-flop,

I would still recommend leaving the reset signal in the design.  If you run out of

pins or routing resources, then you can just tie the reset signal inactive in your

schematic or HDL.  The tools will take care of removing the unused resources.

 

4) Bob explained the supply and ground pins fairly well.  Bottom line - connect them all!

Even if your design runs at a low frequency, the edge rates on the I/O pins will be very

fast - much faster than TTL.  It is these edge rates that cause "ground bounce" due

to their very high frequency components.  Also the bulk of the internal power used

by the device is dynamic as well, due to internal capacitance on switching nodes.

So the internal power and ground need low inductance paths to the power planes

as well.  Basically you must hook up all power/ground pins and you must bypass

them with high-speed decoupling caps.  Otherwise regardless of the frequency of

the design the chip can suddenly stop working - including losing its internal configuration.

 

-- Gabor

-- Gabor
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Re: home-brew CPU on a CPLD

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Hi Bob!

 

Thank you for your reply. Firstly, I kind of appologize for my stupid question regarding all the supply pins. I should have known better. Secondly, I especially appreciate the solution to my buffer-problem. At first I didn't understand what you meant but now I think I actually do. But tieing them together pin-wise will not suffice. Even though that also seems to be a solution.

 

By the way, I liked your description of my "weird" glitch :-) But as I recon this can still be a working design approach. I use this asyncronous glitch everyhere in my counters and registers.

 

Another beginners question, what is the difference between a CPLD (Complex Programmable Logic Device, I guess) and a FPGA (Field Programmable Gate Array, I guess)?

 

Finally, your answer made very much sense. Thank you again!

 

Kind regards, Roger Knopp

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