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Visitor
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8,781 Views
Registered: ‎09-11-2007

parallel flash programming

Hi,

I found this article

http://www.altera.com/products/devices/cpld/max2/applications/bridge/mx2-jtag_translator.html

which describes how to use JTAG and CPLD to programm parallel flash memory chip -

and i'm wondering - it is possible to make something like this, using XC2 device ?

More common - how to blink LED ,connected to CPLD, using JTAG interface?

regards,

Stefan

 

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Visitor
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8,769 Views
Registered: ‎08-12-2009

Re: parallel flash programming

1) Yes, you can program a parallel flash connected to a CPLD (or any JTAG-compliant device) using boundary-scan. For example, TopJTAG Flash Programmer can do this.

 

2) You can use TopJTAG Probe to monitor and control pins of a CPLD using boundary-scan.

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Visitor
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8,760 Views
Registered: ‎09-11-2007

Re: parallel flash programming

Hi, Zgora,

Thank You for links!

I checked these sites, it seems - TopJTAG Flash Programmer  works with AMD ... Intel  flash memories. I want  Atmel :) .

Anyway -

"By utilizing boundary-scan (JTAG) test logic on a chip connected to flash memory (e.g. CPU, FPGA, ASIC), TopJTAG Flash Programmer 'detaches' the chip's core from its pins and manipulates pins values in order to communicate with flash memory"

 

this sentence describes how LED can be blinked - needed is good knowledge of JTAG "language". 

I'll continue to investigate.

regards 

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Registered: ‎08-12-2009

Re: parallel flash programming

Most parallel NOR flash memories in the market today are compatible with either AMD or Intel command sets (command sequences to perform operations like erase, program, read device id, etc.). Atmel is not the exception. So TopJTAG Flash Programmer can program most of the parallel NOR flash memories including those from Atmel.

 

If you want to blink LEDs, the best options is to use TopJTAG Probe software. It's quite easy to use. When device is in a SAMPLE mode (SAMPLE instruction is loaded into JTAG Instruction Register)  you can monitor states of device's pins, i.e. TopJTAG Probe works like a slow logic analyzer in this mode. When device is in an EXTEST mode, the device's core is "disconnected" from its pins and pin states are controlled from software by reading and writing boundary-scan register. In this mode you can set signal values on output and bidirectional pins and monitor pin values on input pins.

 

Please note: BSDL files provided by Xilinx are intended for pre-configured devices. If you wish to use boundary-scan on a configured CPLD, the default BSDL file must be modified. Xilinx provides BSDLanno program (a part of ISE suite) which can generate a BSDL file specific for the particular design. More about BSDLanno is here: http://www.xilinx.com/support/answers/15346.htm. However, probably, the easiest solution is just to erase a CPLD and use the default BSDL file which is supplied by Xilinx (comes with ISE installation).

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Registered: ‎09-11-2007

Re: parallel flash programming

Hi Zgora,

Thank You for letter! It is very informative for dummie like me.

I just read AM29f010 and AT29C010 docs. Atmel's chip is small sector, programming sequence is 3(6)+128 bytes. AMD is big sector, programming sequence is (3+1)*N bytes. I did not know any AMD or Intel small sector chips . So in this case Atmel chip can be exception, i am not sure.

Yesterday i read some papers and now i'm little bit more informed about JTAG. Parallel flash progamming is just piece of common testing and production problems.  In our work we use this very little  and it is not very clear as internal mechanism. 

On other hand - for me is interesting as common way to build some type of programmer - let say for parallel flash, serial flash , PIC processor and any new unknown reprogrammable device. In this case is needed (i think) JTAG software, which can execute some macrosses.  Other side is speed.  I see xc2c64vq100 has 192 bits to shift.   It will be slow process if for every bit change (for exampe CLK line to SPI flash) i must send 192 bits via JTAG. So i think - only 1(or max 3)  bit is sended  ( if that CLK pin is first in chain), and JTAG state machine is changed to expose changes on pins. I'm right? More - to send one byte to AMD29010 flash 16 address ,8 data , 3 control bits must be changed many times - maybe it is possible to preprogram some state machine in CPLD and drive it trough JTAG ? ... I'll continue to read.

regards

 

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Registered: ‎08-12-2009

Re: parallel flash programming

You are right, unfortunately, AT29C010 is the exception, its command set is not compatible with AMD or Intel. Moreover, as each byte to be programmed must be supplyed withing 150 us from the previous byte, this flash memory cannot be programmed using boundary-scan. This is because when sending data from a PC over USB or parallel port cable you cannot guarantee that every byte comes no later then 150 us after previous byte.

 

You also right about boundary-scan is slow. However, if you need to program a few kilobyte bootloader code boundary-scan programming can be a good choice. Boundary-scan programming is universal and works with any JTAG-compliant device.
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