01-24-2011 07:52 AM
I am reading the Timing Model in DS090 for Coolrunner II, but I can't find the "Register asynchronous S/R recovery before clock" (tRAI)
Is it not applicable anymore?
02-10-2011 01:42 AM
Solved. This is the answer from helpdesk:
We dont have a Trai value for the Coolrunner-II. But the "safe to use" value for Trai would be to copy the Taprpw for the density/speed grade.
01-26-2011 04:37 AM
The reason I am asking is that I'm porting code from a XC9500 to a Coolrunner 2 (XC2C128-7)
The design includes a VME bus slave, where the interface is designed asynchronously. The data strobe input is fed to the S/R pin of a FF, while a delayed version of this strobe signal is fed to the clock input of the same FF.
The Clk input needs to be sufficiently delayed so that the FF has time to recover after the reset (the clock edge cannot occur instantly after releasing the reset due to tRAI).
The reset recovery time (tRAI) is 10 ns for the XC95144XL-10
http://www.xilinx.com/support/documentation/data_sheets/ds056.pdf
but I can't find the tRAI for my XC2C128 here:
http://www.xilinx.com/support/documentation/data_sheets/ds093.pdf
Why? Am I missing fundamental changes to the architecture?
Best Regards,
Steffen Forså
02-10-2011 01:42 AM
Solved. This is the answer from helpdesk:
We dont have a Trai value for the Coolrunner-II. But the "safe to use" value for Trai would be to copy the Taprpw for the density/speed grade.