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Visitor
Visitor
3,279 Views
Registered: ‎03-24-2014

slow to fast clock data latching

dear all, 

 

i want to know if there is a way to latch the serial data arriving at the coolrunner CPLD (at 115200bps baud rate) to a higher clock which FPGA expects(around 10 MHz) continuously without storing much of the data.(no flash memory used). i have 256 macro cells in the CPLD.

 

could anyone give suggestions for the same?

thenk you!

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Observer
Observer
3,024 Views
Registered: ‎04-11-2008

Re: slow to fast clock data latching

As I understand, the CPLD is clocked at 10MHz, and the data is 115200 bps.  In that case, a UART is what you need.  I beilive that Xilinx has UART code on its site.  If not, then check the web, especially opencores.com

 

-Dave Pollum

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Moderator
Moderator
2,961 Views
Registered: ‎01-15-2008

Re: slow to fast clock data latching

As mentioned by Dave, check the following link for the UART application note also you can check for the reference design in the same doc

http://www.xilinx.com/support/documentation/application_notes/xapp341.pdf

 

--Krishna

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