03-27-2014 03:33 AM
i want to know if there is a way to latch the serial data arriving at the coolrunner CPLD (at 115200bps baud rate) to a higher clock which FPGA expects(around 10 MHz) continuously without storing much of the data.(no flash memory used). i have 256 macro cells in the CPLD.
could anyone give suggestions for the same?
04-21-2014 06:05 AM
As I understand, the CPLD is clocked at 10MHz, and the data is 115200 bps. In that case, a UART is what you need. I beilive that Xilinx has UART code on its site. If not, then check the web, especially opencores.com
05-08-2014 06:32 AM
As mentioned by Dave, check the following link for the UART application note also you can check for the reference design in the same doc