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Adventurer
Adventurer
789 Views
Registered: ‎02-24-2009

Artix-7 daisy chain issue

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One of my customers is using two A75T's in daisy chain.

With write_cfgmem they have created a BIN file:

 

write_cfgmem -force -format BIN -size 16 -interface SPIx1 -loadbit \

"up 0x0 D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit \

up 0x400000 D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit" \

-file D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main_flash_201800801

 

Output of Vivado:

 

Command: write_cfgmem -force -format BIN -size 16 -interface SPIx1 -loadbit {up 0x0 D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit  up 0x400000 D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit} -file D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main_flash_201800801

Creating config memory files...

Creating bitstream load up from address 0x00000000

Loading bitfile D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit

Creating bitstream load up from address 0x00400000

Loading bitfile D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit

Writing file D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main_flash_201800801.bin

Writing log file D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main_flash_201800801.prm

===================================

Configuration Memory information

===================================

File Format        BIN

Interface          SPIX1

Size               16M

Start Address      0x00000000

End Address        0x00FFFFFF

 

Addr1         Addr2         Date                    File(s)

0x00000000    0x003A607B    Jul 31 14:11:22 2018    D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit

0x00400000    0x007A607B    Jul 31 14:11:22 2018    D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit

0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.

write_cfgmem completed successfully

 

Problem is that the second Artix-7 never receives data. The first Artix-7 is configured but because the DONE is pulled low by the second one, it will not go through the start-up sequence.

 

Dis we miss something?

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
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1 Solution

Accepted Solutions
Adventurer
Adventurer
735 Views
Registered: ‎02-24-2009

Re: Artix-7 daisy chain issue

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Hi Bhushan,

 

It is now working.

May I point to the documentation UG470 where the example is wrong.

UG470 (v1.13.1) August 20, 2018 page 81 / PROM Files for Serial Daisy Chains, there is the WRITE_CFGMEM Tcl command, use the argument -loadbit "up|down <address1> <bitfile1.bit> <address2> <bitfile2.bit>". Refer to software documentation for

details.  

Also in other documentation it is described wrong.

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
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5 Replies
Xilinx Employee
Xilinx Employee
773 Views
Registered: ‎03-07-2018

Re: Artix-7 daisy chain issue

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Hi @kvanegmond

 

Does customer schematic matches figure below? (Note: DONE,INIT_B are common and pulled up HIGH)

Slave serial mode Daisy mode Config.png

 

Provide status register details

 

Regards,

Bhushan

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Regards,
Bhushan

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Adventurer
Adventurer
763 Views
Registered: ‎02-24-2009

Re: Artix-7 daisy chain issue

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Hi Brushan,

 

Yes, this is exactly the schematic that was used.

It is confirmed that FPGA1 is loaded. When he programs FPGA2 trough JTAG and refreshes FPGA1 trough JTAG then everything is working.

When he examined DOUT FPGA1 during boot with a scope then nothing happens.

 

He thinks there is something missing in the TCL command. When he compares the generated BIN or MCS file then there is no difference in the 'single' or 'double' situation.

The file is identical started at address 0x0 in the single and double situation.

Starting at address 0x400000 there is the image for FPGA2 which is also exactly identical to the image starting at 0x0 or the singe file.

It seems a command is missing the let the chain know that there are two FPGA's and to make DOUT active.

No real example can be found for this situation.

Enclosed is a zip file with bout a single and double bitstream that will show the above.

 

What log file do you want to see, the log file for generating the BIN/MSC file was in the original massage.

 

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
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Xilinx Employee
Xilinx Employee
750 Views
Registered: ‎01-10-2012

Re: Artix-7 daisy chain issue

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Hi @kvanegmond

 

For daisy chains the bit files needs to be concatenated, you shouldn't specify the address.

So please recheck by generating mcs/bin using below command

 

write_cfgmem -force -format BIN -size 16 -interface SPIx1 -loadbit \

"up 0x0 D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit \

 D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main.bit" \

-file D:/Data/Chroma/HDAWDG/Xilinx/HDAWDG/HDAWDG.runs/impl_1/HDAWDG_main_flash_201800801

Adventurer
Adventurer
736 Views
Registered: ‎02-24-2009

Re: Artix-7 daisy chain issue

Jump to solution

Hi Bhushan,

 

It is now working.

May I point to the documentation UG470 where the example is wrong.

UG470 (v1.13.1) August 20, 2018 page 81 / PROM Files for Serial Daisy Chains, there is the WRITE_CFGMEM Tcl command, use the argument -loadbit "up|down <address1> <bitfile1.bit> <address2> <bitfile2.bit>". Refer to software documentation for

details.  

Also in other documentation it is described wrong.

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
0 Kudos
Visitor xiaohetao
Visitor
363 Views
Registered: ‎12-28-2018

Re: Artix-7 daisy chain issue

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can you post your solution. thank you.
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