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Observer yuko.2828
Observer
724 Views
Registered: ‎12-27-2018

Boundary Scan for Xilinx FPGA

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Hi all !! Happy new year !

We are planning to create a prototype board using Xilinx FPGA (ZYNQ-7000).
I want to do JTAG boundary scan to test my FPGA during board mass productions. 

Newbie questions :
1. What kind of ZYNQ-7000 pin can be accessed/tested using JTAG boundary scan ?
2. Is there any document available to give me some  basic knowledge regarding boundary scan ?

Hi Moderators !
Please move my post to appropriate board.

Thanks a lot !
Y.

 

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1 Solution

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Xilinx Employee
Xilinx Employee
665 Views
Registered: ‎08-10-2008

回复: Boundary Scan for Xilinx FPGA

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Hi,

 

Download the BSDL file for the part you are using; all the pins described in the file can be accessed by JTAG.

To learn this basic knowledge of BS, I suggest you read IEEE 1149.1 protocol. This may not be provided for free but you can try to register in the IEEE web first.

Xilinx does not have much info about BS.

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2 Replies
Xilinx Employee
Xilinx Employee
666 Views
Registered: ‎08-10-2008

回复: Boundary Scan for Xilinx FPGA

Jump to solution

Hi,

 

Download the BSDL file for the part you are using; all the pins described in the file can be accessed by JTAG.

To learn this basic knowledge of BS, I suggest you read IEEE 1149.1 protocol. This may not be provided for free but you can try to register in the IEEE web first.

Xilinx does not have much info about BS.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------
Observer yuko.2828
Observer
644 Views
Registered: ‎12-27-2018

回复: Boundary Scan for Xilinx FPGA

Jump to solution

@iguo Thank you ! 謝謝 !
Can I give you 3 kudos ?

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