08-12-2019 04:35 AM
For kintex-7FPGA, since I am run out programmed power channels, can I connect the VCCO_0 of bank0 to the VCCO of other banks. The IO will run at 1.2V. But VCCO_0 should be equal or above 1.5V. I think if I could program FPGA using slave selectmap method and set the VCCO to 1.5V. After configuration, I set the VCCO to 1.2V for using. It means VCCO_0 will be 1.2V because VCCO of all banks are connected together. The pull up resistors in bank 0 will be pull to 1.2V too, including pull up resistor for mode pin, program_b, done, init_b, etc. Is this idea work?
08-12-2019 06:45 AM
not saying it will work but just that I cannot see a problem so far you keep VCCINT stable that is what keeps your configuration.
I assume (haven't checked it) that 1V2 is in the range for VCCO_0, besides the configuration requirements
08-12-2019 07:27 AM
08-12-2019 09:56 AM
suggest you double check the data sheet, I dont have them to hand,
As far as I know, the control pin is not just used during configuration , but before and after configuration it has to be valid.
what do yo have the control pin set to ?
08-12-2019 07:54 PM
I will set CFGBVS to 0 because the VCCO_0 is 1.5V when configuration.
08-12-2019 09:26 PM
If not in configuration, can I set VCCO of bank 14 and bank 15 diffferent than VCCO_0? That mean keep VCCO_0 at 1.5V and set VCCO_14 and VCCO_15 to 1.2V after configuration. VCCO of bank 0,14,15 are equal at 1.5V before and during configuration.
08-12-2019 11:52 PM
I dont know if you can move the powers around like this .. this is way outside normal ..
As its so un usual, can you go into a bit more detail as to why you want do this please ?