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Visitor michail
Visitor
79 Views
Registered: ‎05-14-2019

Direct SPI programming with 7-series FPGA

How to force 7-series FPGA configuration interface in SPI mode to high impedance state correctly? With 6-series and prior the simple way was to ground the PROGRAM_B line by programming cable fixed wiring. Unfortunately the 7-series PROGRAM_B is not level sensitive anymore. Grounding INIT_B delays configuration if grounded before power-up, but does it disable all FPGA SPI config outputs? I need a safe way to disable FPGA config outputs (to access SPI config memory) in all following cases: 1. The board is power up with programming cable already connected (in a factory). 2. The cable is connected to the board already powered up trying to load configuration from empty SPI memory (i.e. in the factory or lab) 3. The cable is connected to the board already powered and FPGA already configured from previously programmed SPI memory (in lab update). The on-board SPI access should be simple connector accessing SPI interface and other FPGA config pins if necessary. Definitely not a midway CPLD. I need to utilize direct SPI programming method because indirect access using JTAG is both impractical for production and will not work for updates 10+ years later when 7-series FPGA won't be supported by Xilinx tools anymore and old tool versions unable to run on computers and OS of the time. I'm designing a product with 20 years life cycle.
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Xilinx Employee
Xilinx Employee
53 Views
Registered: ‎03-07-2018

Re: Direct SPI programming with 7-series FPGA

Hello @michail 

For 7-series FPGA UG470 mentions following guidelines for delaying FPGA configuration with SPI Flash:

SPI Guidelines.png

For direct programming flash you need to use third party spi flash programmer as 7-series FPGA support indirect flash programming only.

I need a safe way to disable FPGA config outputs (to access SPI config memory)  > FPGA will not sent configuration commands to SPI untill INIT_B goes high.

 

 

Regards,
Bhushan

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Visitor michail
Visitor
40 Views
Registered: ‎05-14-2019

Re: Direct SPI programming with 7-series FPGA

"FPGA will not sent configuration commands to SPI until INIT_B goes high." What I cannot find in any UG or DS is clear statement whether FPGA config pins towards SPI are all high-Z or actively driven inactive state until the INIT_B goes high. That is substantial difference for any direct access to SPI memory.
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