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Visitor scs-kno
Registered: ‎11-30-2018

Duration/Periodicity of Readback CRC

Hi all!

We have a Spartan 6 (XC6SLX75-3FGG484I) and need to continuously monitor the Readback CRC value as described in UG380. For realiability reasons, we periodically trigger an error by changing the PLL.

How long does it at most take for this change to be visible on INIT_B?

I'm looking for something similar to Table 9-6 in Altera's CYIV-51009-1.3.

Thank you!

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Xilinx Employee
Xilinx Employee
Registered: ‎08-10-2008

回复: Duration/Periodicity of Readback CRC

What do you mean by 'trigger an error by changing the PLL'? Did you modify PLL settings by DRP port?

If so, this does not count a bit flip, which cannot trigger a readback error. To inject an error you need scrubbing or error injection by SEM IP. That's a big topic to discuss. Contact the local support first if possible.

Don't forget to reply, kudo, and accept as solution.
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