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Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

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Visitor
Posts: 6
Registered: ‎01-12-2018

Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

[ Edited ]

Hello,

I would like to ask if there is possibility to erase, dump flash memory attached to Zynqu device using Vivado IDE GUI or command line when having Xilinx JTAG programmer attached.

 

I develop SW area and want to make test with changing FSBL/uBoot location. 

We want to read, write and program it by JTAG directly, without usage of Linux command.

 

BR

 

 

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Moderator
Posts: 214
Registered: ‎04-12-2017

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

Hello @stawowcz,

 

It can be done using the hardware manager of the VIVADO.

erase.PNG

 

while programming the file to the configuration memory select ERASE option only.

Thank you.

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Visitor
Posts: 6
Registered: ‎01-12-2018

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

Hi 

Could You provide tutorial that is more extended?

It means from the beginning to the end, step by step?:) 

 

Visitor
Posts: 6
Registered: ‎01-12-2018

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

Additionally

After installing 

Vivado Design Suite 2017.3 Update 1 is now available with support for Production Zynq UltraScale+ MPSoC -1L/-2L Devices: ZU2EG/CG, ZU3EG/CG, ZU6EG/CG, ZU9EG/CG, ZU15EG; Production Kintex UltraScale+ FPGA -1L/-2L Devices: KU9P, KU13P; Production Virtex UltraScale+ FPGA -2L Devices: VU3P, VU5P, VU7P, VU9P, VU11P, VU13P. For customers using these devices, Xilinx recommends installing Vivado 2017.3.1.  For other devices, please continue to use Vivado 2017.3.

NOTE: This update must be applied to an existing installation of Vivado 2017.3.  After updating, the Vivado version will be 2017.3.1.

 

There is still not  Zynq board on vivado:

 

Screen in attachments

 

No Zynq.PNG
Xilinx Employee
Posts: 1,948
Registered: ‎07-23-2012

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

If your sole intention is to program (or erase or verify) the flash, you can install Vivado Lab Edition; it comes with Vivado HW manager using with you should be able to meet your requirement.

 

Here is the link for that https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2017-3.html 

 

For the tutorial, you may refer to https://www.youtube.com/watch?v=IIAZEXPlwtc ; this flow is applicable for Zynq too. 

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Moderator
Posts: 214
Registered: ‎04-12-2017

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

[ Edited ]

Hello @stawowcz,

 

Please follow the below procedure:

1. Install the latest version of VIVADOO design suite or Labtools.

2. Open the hardware manager and connect the board via JTAG to it.

3. After connecting the board right click on the device name and add the configuration memory device. Chose the part which has        been used on the evaluation board.

4. It will be listed below the Xilinx device in a hierarchy. After that right click on the memory part and select programming option.

5. The you will see the window as mentioned in my previous reply. From that select only the erase option to erase the part.

 

make sure that memory configuration part used on your board is supported by VIVADO. refer UG908.

Hope this helps.

Thank you.

 

 

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Visitor
Posts: 6
Registered: ‎01-12-2018

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

When I program I got message(after 100% of progress)

[Labtools 27-3165] End of startup status: LOW

 

Low.PNG
Visitor
Posts: 6
Registered: ‎01-12-2018

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

Now I am in here.

 

 

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Visitor
Posts: 6
Registered: ‎01-12-2018

Re: Erase, dump, flash memory attached to Zynq device using Vivado IDE GUI or command line having Xilinx JTAG programmer attached

Console output after programing board:

start_gui
open_project C:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.xpr
open_project C:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.3/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'design_1_auto_pc_0' generated file not found 'c:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_auto_pc_0' generated file not found 'c:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_auto_pc_0' generated file not found 'c:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_auto_pc_0' generated file not found 'c:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'design_1_auto_pc_0' generated file not found 'c:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_sim_netlist.vhdl'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 1083.824 ; gain = 391.500
update_compile_order -fileset sources_1
open_bd_design {C:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/design_1.bd}
Adding cell -- xilinx.com:ip:zynq_ultra_ps_e:3.1 - zynq_ultra_ps_e_0
Adding cell -- xilinx.com:ip:axi_gpio:2.0 - axi_gpio_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_96M
Adding cell -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Successfully read diagram <design_1> from BD file <C:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/design_1.bd>
open_bd_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1083.824 ; gain = 0.000
open_hw
connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.3.1
**** Build date : Oct 20 2017-14:35:11
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


current_hw_target [get_hw_targets */xilinx_tcf/Xilinx/000018dd3fb801]
set_property PARAM.FREQUENCY 6000000 [get_hw_targets */xilinx_tcf/Xilinx/000018dd3fb801]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000018dd3fb801
open_hw_target: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1422.086 ; gain = 338.262
set_property PROGRAM.FILE {C:\ftproot\rfsw_full_flash_image.bin} [get_hw_devices xczu15_0]
current_hw_device [get_hw_devices xczu15_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xczu15_0] 0]
INFO: [Labtools 27-1435] Device xczu15 (JTAG device index = 0) is not programmed (DONE status = 0).
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {mt25ql64-qspi-x4-single}] 0]
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu15_0]
open_bd_design {C:/Users/rfswtest/AppData/Roaming/Xilinx/Vivado/SWUP_1/project_tutorial/project_tutorial.srcs/sources_1/bd/design_1/design_1.bd}
disconnect_hw_server localhost:3121
connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
current_hw_target [get_hw_targets */xilinx_tcf/Xilinx/000018dd3fb801]
set_property PARAM.FREQUENCY 6000000 [get_hw_targets */xilinx_tcf/Xilinx/000018dd3fb801]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000018dd3fb801
set_property PROGRAM.FILE {C:\ftproot\rfsw_full_flash_image.bin} [get_hw_devices xczu15_0]
current_hw_device [get_hw_devices xczu15_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xczu15_0] 0]
INFO: [Labtools 27-1435] Device xczu15 (JTAG device index = 0) is not programmed (DONE status = 0).
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {mt25ql64-qspi-x4-single}] 0]
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu15_0]
set_property PROBES.FILE {} [get_hw_devices xczu15_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xczu15_0]
set_property PROGRAM.FILE {C:/ftproot/BB_FPGA_top.bit} [get_hw_devices xczu15_0]
program_hw_devices [get_hw_devices xczu15_0]
ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitstream was generated for part xczu15eg-ffvb1156-2-i-es1, target device (with IDCODE revision 1) is compatible with production revision bitstreams.
To allow the bitstream to be programmed to the device, use "set_param xicom.use_bitstream_version_check false" tcl command.
ERROR: [Labtools 27-3165] End of startup status: LOW
ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.
set_property PROBES.FILE {} [get_hw_devices xczu15_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xczu15_0]
set_property PROGRAM.FILE {C:/ftproot/boot.bin} [get_hw_devices xczu15_0]
program_hw_devices [get_hw_devices xczu15_0]
ERROR: [Labtools 27-3165] End of startup status: LOW

 

Console output after memory device programming:

set_property CFGMEM_PART {mt25qu01g-qspi-x4-single} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.ADDRESS_RANGE {entire_device} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.FILES [list "C:/ftproot/boot.bin" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.ZYNQ_FSBL {C:/fsbl.elf} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
startgroup
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xczu15_0] 0]]
INFO: [Xicom 50-104] The verify operation will only be performed on the address range specified by the Memory Configuration File (MCS).
Problem in running uboot
Flash programming initialization failed.
ERROR: [Labtools 27-3161] Flash Programming Unsuccessful
program_hw_cfgmem: Time (s): cpu = 00:00:00 ; elapsed = 00:00:34 . Memory (MB): peak = 1613.078 ; gain = 0.000
ERROR: [Common 17-39] 'program_hw_cfgmem' failed due to earlier errors.

 

 

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