08-06-2019 05:18 AM
Im trying to configuring the FPGA Spartran-6 through imx6q sabresd processor using slave serial mode.
Im able to send bin data bit-by-bit to FPGA. but, DONE pin is not going HIGH.
Please help me.
08-06-2019 11:29 AM
Is the configuration file compressed? Is it possible to look at the oscilloscope and compare the timings of the configuration?
08-06-2019 05:25 PM
You might want to review this reference:
http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf (Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode)
and note the # of extra CCLK cycles potentially required here.
(this is the updated version for 7 series but conceptually is very similar if I remember right: http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf (Using a Microprocessor to Configure 7 Series FPGAs via Slave Serial or Slave SelectMAP Mode)
08-06-2019 07:13 PM
Can you check if the timing is same as figure 2-4 in ug380 at:
For example, bit sequence you sent. What's the CCLK frequency? Do you continually send more CCLK after data was delievered? Is the JTAG programing successful?
08-07-2019 02:18 AM
Hi,Thank you so much for response.
Actually im generating the clock of 250khz and after sending all bit data, waiting for DONE become high and concurrently generating the clock until DONE pin become high. but, DONE pin is not at all going high even i wait for a long period of time.
08-07-2019 06:30 AM
CCLK generating by the processor has a frequency of 450khz is it fine for data transmission?
I'm using .Bin file which not byte-swapped in slave serial mode, do I need any other files for this process?
08-07-2019 11:37 AM
Here’s some things to do and check for slave-serial configuration of a Spartan-6:
08-20-2019 04:56 AM
Thank you so much for reply,
Im doing the same thing but still its not configuring FPGA. Is there any other way to make it work?