05-10-2015 07:39 AM
I've read anything I could about Partial Reconfiguration, but I still have many doubts.
What I'm trying to do is the following:
I have to do these operations on the Zynq Z-7020 without involving the CPU (PS), but only with the PL.
Is that even possible?
I must note that it is very important that the PL is able to perform some operations on the partial bitstream before loading it into the FPGA.
Thanks in advance
05-10-2015 08:07 AM
What you descibe is all possible. I suggest you start by working all the design exercises in:
and examine all the demo designs for a zedboard, or Zynq board of your choice.
The Zynq procesor system starts up with exclusive control of the programmable logic. After the initial load, the processor may be programmed to turn over control. The PL may then with a design as you descibe, take over.
05-10-2015 10:06 AM
Thanks for the reply.
What I have understood so far is: