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Explorer
Explorer
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Registered: ‎12-12-2009

How to simulate STARTUPE2 primitive for Artix-7

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I am trying to read from Quad-SPI Flash device on Digilent Nexys A7 board. Reference manual includes the following statements:

All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2.

In order to understand how STARTUPE2 works, first I want to simulate STARTUPE2.

The following figure* shows how to drive the pins of STARTUPE2 primitive of Kintex-7 device:

Screen Shot 2019-03-27 at 17.15.14.png

When I instantiate STARTUPE2 primitive for Artix-7 in my design (as described in UG768 and in the figure above) and try to drive spi_clk pin from my SPI controller, the spi_clk pin remains at 'Z' during the whole simulation although my SPI controller sends either logic-0 or logic-1 to spi_clk pin.

What is the correct way to generate a proper clock signal to drive the clock pin of the SPI Flash in this case?

abdullah
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Moderator
Moderator
188 Views
Registered: ‎06-05-2013

Re: How to simulate STARTUPE2 primitive for Artix-7

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Please refer to the UG#470 7 series configuration user guide page#94-96.(https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf)
Yes, you can provide a SPI clock via the STARTUP primitive's USRCLKO from the FPGA fabric. Check this AR as well https://www.xilinx.com/support/answers/52626.html
Similar question answered: https://forums.xilinx.com/t5/Simulation-and-Verification/Access-to-CCLK-in-Simulation/td-p/514811
Thanks
Harshit
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1 Reply
Moderator
Moderator
189 Views
Registered: ‎06-05-2013

Re: How to simulate STARTUPE2 primitive for Artix-7

Jump to solution
Please refer to the UG#470 7 series configuration user guide page#94-96.(https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf)
Yes, you can provide a SPI clock via the STARTUP primitive's USRCLKO from the FPGA fabric. Check this AR as well https://www.xilinx.com/support/answers/52626.html
Similar question answered: https://forums.xilinx.com/t5/Simulation-and-Verification/Access-to-CCLK-in-Simulation/td-p/514811
Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------