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Registered: ‎09-05-2018

[Labtools 27-3165] error, but FPGA is programmed?!

I am using the VC707 Eval board.  When I power-up the board using the default FPGA configuration, the HW Manager connects and I can pull up the XADC dashboard.  All seems well. 

When I re-program the device with my own bitstream, I get the "[Labtools 27-3165] End of startup status:  LOW" error.  However, the DONE LED is lit, and I know my design is loaded since I added logic that flashes two of the user LEDs in a pattern.  This also means the clock is present.  There is only one clock (100 MHz - derived from on-board 200 MHz system clock) in my design and it also goes to the ILA I added to the design.  Changing JTAG clock didn't help.  Refreshing the device results in "[Labtools 27-2312] Device xc7vx485t_0 is no longer available." error.  Disconnecting and reconnecting the server, and then trying Auto Connect results in "[Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210203A3D1ADA" error.

Somehow programming my own device causes the device to disappear from the HW Manager.  I know the USB cable is good since it works with the default design.  SW11 DIP switch is set to JTAG mode.  Laptop connected to VC707 is running Win10 with Vivado 2018.2.  Any help is appreciated.




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4 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎06-06-2018

Re: [Labtools 27-3165] error, but FPGA is programmed?!

Hi @dblogicdesign,

1. Ensure all the voltage rails all above respective Threshold levels and probe all the rails and ensure that there is no dip in any of the rails at start up and during configuration.

    Ensure all clock and data lines are free from Signal Integrity issues.

2. Please try reinstalling the Drivers by referring this https://www.xilinx.com/support/answers/59128.html.

3. Provide more CCLK clock cycles(10 or more) after DONE pin goes high, till EOS is asserted.

4. Try reducing the JTAG clock frequency to 3Mhz and try configuring the device.

5. Share status Register values.

6. If you have another VC707 board try detecting and configuring the device and also try with other JTAG Cable.



Deepak D N


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Registered: ‎01-16-2013

Re: [Labtools 27-3165] error, but FPGA is programmed?!


As per your information there is free running clock and your design works on single clock i.e. 100MHz.

The only problem I see here is the ILA clock, ILA clock should be 2x of data clock (i.e. 200MHz).

Use 200MHz system clock and get two clocks as output using MMCM/PLL i.e. 100MHZ (divide by 2) and 200MHz (i.e. divide by 1). Run your design using 100MHz clock and provide 200MHz (MMCM generated clock) to ILA clock input.

Let me know if this helps.




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Registered: ‎09-05-2018

Re: [Labtools 27-3165] error, but FPGA is programmed?!

Thanks for the suggestion Yash.  I tried it, although I don't quite understand the reasoning.  All my signals going to the ILA are clocked by my 100 MHz clock.  This is the clock domain I chose for these signals in the wizard when adding my ILA.  I created a 200 MHz clock out of the MMCM I was using, and chose it as the domain for the debug signals, but I didn't see how this would help.  And it didn't.

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Registered: ‎09-05-2018

Re: [Labtools 27-3165] error, but FPGA is programmed?!

Here is what happens when I re-program the device:

set_property PROBES.FILE {.....model_3.ltx} [get_hw_devices xc7vx485t_0]
set_property FULL_PROBES.FILE {.....model_3.ltx} [get_hw_devices xc7vx485t_0]
set_property PROGRAM.FILE {.....model_3.bit} [get_hw_devices xc7vx485t_0]
program_hw_devices -disable_eos_check [get_hw_devices xc7vx485t_0]
program_hw_devices: Time (s): cpu = 00:00:55 ; elapsed = 00:00:55 . Memory (MB): peak = 3160.941 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0]
ERROR: [Labtools 27-2312] Device xc7vx485t_0 is no longer available.
Check cable connectivity and that the target board is powered up then
use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target.
Use open_hw_target to re-register the hardware device.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203A3D1ADA

As I stated before, disconnecting from the server and re-connecting doesn't work.  I still can't see the device.  The above was an attempt with JTAG clock at 3 MHz.  I've tried two different cables.  Both can access the board fine BEFORE I download my bit file.  Again, the device is getting programmed, as I see the two user IDs flashing per my design, yet the device disappears from the JTAG chain.

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