UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer nate.wang
Observer
186 Views
Registered: ‎03-04-2013

[Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

Hi all,

I designed a small PCB that daisy trained four JTAG devices as the below figure.

I can successfully perform configuration on both the NOR flash attached beside xc7k325t, however, if I try to perform configuration on the NOR flash beside xc7a200t I got error as below : 

[Labtools 27-3291]2.png

I have tried to slow down TCK frequency to 10MHz and even 1MHz, but still got exactly the same error. Below is the waveform at 1MHz(yellow : TCK / green : TDI / blue : TDO), I believe this is not a signal integrity problem.

scope_10.png

It is strange that If I remove one of the xc7k325t on the JTAG train, configuration on both of the xc7a200t is normal.

I am sure the NOR flash attaced beside xc7a200t is S25FL128Sxxxx0, not S25FL256Sxxxx1, so why Vivado would detect the wrong flash part in some cases that preventing the configurtion process ?

thanks.

0 Kudos
6 Replies
169 Views
Registered: ‎01-22-2015

Re: [Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

@nate.wang 

Please show here the schematic of your pcb with 5 JTAG connectors (which appeared in another of your posts).  Please tell us:

  1. why you are using U2 (digital level translator)
  2. why VREF on U1 is connected to 2V5
  3. does oscope show that JTAG timing specifications in Fig 3-1 of UG470(v1.13.1) are met

Mark

0 Kudos
Observer nate.wang
Observer
156 Views
Registered: ‎03-04-2013

Re: [Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

Hi Mark,

schematic as below

JTAG_sch.png

 

 

  1. why you are using U2 (digital level translator)
  2. why VREF on U1 is connected to 2V5>> in my previous version of xc7a200t board, voltage level of JTAG interface is 2.5V. And because the JTAG interface of my xc7k325t board is 3.3V, I use U2 as voltage level translator to accommedate different voltage levels.
    >> However, in my newest xc7a200t board, I changed the voltage level of JTAG interface from 2.5V to 3.3V, so I had just adjust the VREF of U1 from 2.5V to 3.3V, which leads to much normal operation of FPGA configuration behavior, so I closed my previous post and issued this new post, sorry this was my mistake.
  3. does oscope show that JTAG timing specifications in Fig 3-1 of UG470(v1.13.1) are met

    timing requirement as belowJTAG_timing.pngJTAG_timing2.png

    Please see the picture I attached in this post, I had reduced TCK frequency to 1MHz, meaning there is about 500ns setup/hold time but still got exactly the same error, so I believe timing is not the problem.

 

Appreciate for any futher suggestion, thanks !

0 Kudos
141 Views
Registered: ‎01-22-2015

Re: [Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

…about the voltages:
-just to be clear, I understand from your comments and other post that VREF=J2=J3=3V3.  Is that correct? 

…about VREF:
Typically, VREF is read by the programmer module and used to configure digital IO of the programmer.  Please use oscope to verify digital IO levels coming out of U1, which will probably be 3.3V CMOS levels (because VREF=3V3).  However, U1 driving 2V5 side of U2.  You should check compatibility of 3.3V CMOS and 2.5V CMOS logic.

…about U2:
Since, VREF=J2=J3=3V3, do you really need U2?  It now seems that everything is 3.3V CMOS.  Can you simply remove U2 and wire TMS and TCK straight through?

…about timing:
It matters where in the circuit you measure things.  TCK to TDO should be measured at U1.  TCK to TMS and TCK to TDI should be measured at the J2-J6.  I suspect that U2 was skewing TCK to TDO timing, which is another reason to get rid of U2 if you can.  Did you measure T(TCKTDO) at U1 and find it to be less than the 7ns max?

0 Kudos
Observer nate.wang
Observer
110 Views
Registered: ‎03-04-2013

Re: [Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

Hi Mark,

I removed U2, but still got similar error, then I measured TCKTDO at U1 side at TCK=10MHz as below (yellow : TCK / green : TDO)

TCKTDO_NG_board.png

Since the rising/falling edge of TCK is not sharp enough(I added a EMI bead on TCK in series to filter out glitch signal on TCK) the waveform is possibly violating the 7ns timing requirement(?).

However, I would like to understand the meaning of TCKTDO first, from datasheet of Xilinx FPGA

JTAG_timing.png

Since TDO is an output signal from FPGA, does the time period "TCKTDO" means FPGA outputs its TDO signal within 7ns max after the falling edge of TCK signal ?

Also from datasheet of DIGILENT JTAG-SMT2 module :

Untitled.png

T_HD is 0ns, does this means the JTAG-SMT2 module samples TDO signal right at the falling edge of TCK signal, no hold time is required  ?

If the above description is correct, it looks strange to me that FPGA output TDO and JTAG-SMT2 samples TDO at the same time(ie. TCK falling edge), it is not a reasonable design.

Note that the TDI signal of JTAG-SMT2 is connected to TDI signal of FPGA, and TDO signal of JTAG-SMT2 is connected to TDO signal of FPGA

Untitled.png

 

Really appreciate for the help.

0 Kudos
95 Views
Registered: ‎01-22-2015

Re: [Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

     I would like to understand the meaning of TCKTDO..
I understand TCKTDO to be a clock-to-out time for JTAG.  That is, JTAG is clocking out data on the falling-edge of TCK and the time from this falling edge to the data-change time is a maximum of 7ns.  It is OK if clock-to-out time is less than 7ns.

    …it looks strange to me that FPGA output TDO and JTAG-SMT2 samples TDO at the same time..
Yes, the labelling is strange and confusing.  I think we must refer to inputs and outputs at a JTAG port (and not use the symbols, TDO, TDI etc).  For an output, the JTAG port must obey the clock-to-out time (ie. it can be no more than 7ns).  Remember, clock-to-out time for JTAG is measured from the falling-edge of TCK.  For an input, the observed setup and hold times must be greater than the minimum specified values - and they are measured from the rising-edge of TCK.  

The following document describes timing of JTAG in detail.
https://www.cnblogs.com/shangdawei/p/4753682.html

Perhaps you can again verify that clock-to-out for outputs and setup/hold for inputs is satisfied at all JTAG ports on your board.

    I removed U2, but still got similar error..
Rats!  Table 45 of the datasheet for your flash gives Manufacturer ID (01) and Device ID (hex(18) or hex(17)).  When trying to program the flash, watch the Tcl Console for lines like the following to see what IDs are being reported.

program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
Mfg ID : 20   Memory Type : ba   Memory Capacity : 18   Device ID 1 : 0   Device ID 2 : 0

 

Tags (1)
0 Kudos
Observer nate.wang
Observer
81 Views
Registered: ‎03-04-2013

Re: [Labtools 27-3291] Flash Programming Unsuccessful. Part selected s25fl128sxxxxxx0, but part s25fl256sxxxxxx1 detected.

Hi Mark,

In datasheet of S25FL125/256S the Devie ID is 0x17 / 0x18

Untitled.png

In Vavido I believe the "Device ID" maps to the "Memory Capacity" from TCL console, though its value offsets by 1, 0x18 and 0x19, I guess this is fine.

program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0

program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_2] 0]]
Mfg ID : 1 Memory Type : 2 Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0

After many trail tests, I may find a clue about this error :

10MHz_TCK_series_BLM18AG121SN1-TDI-TDO-TCK3V3_series_BLM18AG121SN1_error.png

At initial all four FPGAs are corretly recognized on JTAG, so I manually assign SPI flashs(S25FL128S on xc7a200t and S25FL256S on xc7k325t) as below :

Untitled.png

FPGA configuration on both of the SPI flashes are successful.

At this time, if I unplug the USB cable of DIGILENT JTAG-SMT2, then pulg back the USB cable again, Vivado automatically re-scan the JTAG chain, and smartly remember the settings(flash ROM type, configuration ROM file...) so the above screen shot appear again without any manual setting.

At this time, if I try to perform configuration on the S25FL128S flash ROM, I got the wrong part selected error as above, then I tried :

  1. on Vivado GUI choose "close target" then "open target", Vivado does not rember the flash ROM type on xc7a200t so I manually set this again(but strangely still remember the name and location of flash ROM file), but I still got the wrong part selected error
  2. close Vivado and execute Vivaso, and manually set flash ROM tyep/flash ROM file, but still still got the wrong part selected error
  3. shut down PC and restart Windows, open Vivado then try again, this works and I can perform FPGA configuration on all devices !

I tried many times so I can confirm the consistency of the phenomonon, just for your reference and thanks for your help !