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Visitor linxinye1
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Registered: ‎07-29-2018

MultiBoot with 7 Series FPGAs Configuration

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      I have a problem in 7 Series FPGAs Configuration. I use a ARM to communicate with FPGA by smc bus, how to load the firmware of FPGA in the QSPI FLASH.
     In the bootloader,  I configure the FPGA pins such as PROGRAM_B,CSI_B,RDWR_B according to the Continuous *8 SelectMAP Data Loading, then loading the bitstream,at the end, judge the state of DONE pin, the state is low, and the state of the INIT_B is high,  what's wrong happened?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: MultiBoot with 7 Series FPGAs Configuration

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You can post your complete STAT register value here.

According to what your said, I guess the FPGA did not recognize any configuration data at all. The most common reason, you did not swap data byte correctly. Search the Config UG for key word 'bit or byte swap' for more details.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: MultiBoot with 7 Series FPGAs Configuration

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You can post your complete STAT register value here.

According to what your said, I guess the FPGA did not recognize any configuration data at all. The most common reason, you did not swap data byte correctly. Search the Config UG for key word 'bit or byte swap' for more details.

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Visitor linxinye1
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Registered: ‎07-29-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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     Byte swap has considered,in hardware,ARM connect with FPGA by D7 to D0,D6 to D1 ...   ARM is Little-Endian, So no extra bit swap needed.

      PROG_B pin low to high , Clear the configuration. CSI_B and RDWR_B is low.  smc controller's writting has no problem, and the data read from the flash is correct. After  Load all the bitstream, the DONE pin is still low and INIT_B pin is high. I doubt  that the bus detection and Sync word haven't recognised.

main Code of  ARM bootloader :

static void load_fpga_continus()
{
    int i,k,ret;
    uint32_t pagesize, lastsize, page_num;
    
    uint8_t tx[PAGE_SIZE];
    
    struct _pin prog_b_pin_output = PROG_B_PIN_OUTPUT;
    struct _pin done_pin_input = DONE_PIN_INPUT;

    struct _pin csi_b_pin_output = CSI_B_PIN_OUTPUT;
    struct _pin rdwr_b_pin_output = RDWR_B_PIN_OUTPUT;

    struct _pin init_b_pin_input = INIT_B_PIN_INPUT;

    dbg_info("****** Init output pin:prog_b rbwr_b csi_b, input pin: init_b done ****** \n");
    pio_set(&prog_b_pin_output); // high
    pio_set(&rdwr_b_pin_output);
    pio_set(&csi_b_pin_output);
    
    smc_pio_configure(&init_b_pin_input, 1);
    smc_pio_configure(&done_pin_input, 1);
        
    dbg_info("******Clear Configuration Memory, pull prog_b low to high ****** \n");
    // low prog_b pin, then pull high
    pio_clear(&prog_b_pin_output);  // low
    mdelay(1);    // min 250ns
    pio_set(&prog_b_pin_output);
    
    // wait for init_b pull high
    while(pio_get(&init_b_pin_input) == 0);

    dbg_info("****** pull down rdwr_b then csi_b ****** \n");
    // low rdwr_b csi_b
    pio_clear(&rdwr_b_pin_output);
    for(i=0;i<100;i++)
    {};
    pio_clear(&csi_b_pin_output);
    
    ret = qspi_loadfpga(FPGA_ADDRESS, HEAD_LEN, tx);
    if(ret)
        dbg_info("Serial flash read error\n");
    else
    {
        display_buf(tx, HEAD_LEN);  // 打印
        for(k=0; k<HEAD_LEN; k++)
        {
            *(volatile uint8_t *)0x80000000 = tx[k];
        }
    }
    ret = qspi_loadfpga((FPGA_ADDRESS + HEAD_LEN), (FPGA_LENGTH - HEAD_LEN), ((uint8_t *)0x80000000));
    if(ret)
        dbg_info("Serial flash read error\n");

    if(pio_get(&done_pin_input) == 1)
    {
        dbg_info("Continus Mode: FPGA load is ok! \n");
    }
    else
    {
        dbg_info("Continus Mode: FPGA load failed! INIT pin state = %x \n", pio_get(&init_b_pin_input));
    }
}

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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Hello @linxinye1

Read configuration registers after configuration (fails or works does not matter) and provide results. 

Properties.png

Regards,
Bhushan

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Visitor linxinye1
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Registered: ‎07-29-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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        Yes,After the configuration. The PROG_B,INIT_B,CSI_B,RDWR_B is high, DONE is low. I can't understand the picture's mean, the FPGA bin is generated by ISE With no swapping.
       Read configuration registers?  not the pins's state?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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Hi @linxinye1

In Impact you can read device status as follows (First single click on FPGA device to select device):

read status in Impact.jpg

Regards,
Bhushan

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Visitor linxinye1
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Registered: ‎07-29-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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      You may misunderstand my meanings, I don't use the JTAG to simulate the FPGA. the firmware of FPGA has already generated, and it has burned into the QSPI FLASH.
      In the flash, using ARM's bootloader to download the configuration image into the FPGA. Just as the ug470 chapter2 SelectMAP Data Loading

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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Hi @linxinye1

I do understand you are performing configuration of FPGA in SelectMAP mode. 

If your FPGA is connected to JTAG then we can read this status register of FPGA after configuration failure in SelectMAP mode and verify at which stage configuration failed and possibly can get root cause.

For more information check https://www.xilinx.com/support/answers/24024.html

Regards,
Bhushan

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Visitor linxinye1
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回复: MultiBoot with 7 Series FPGAs Configuration

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COMMAND: show_config_status 0
INFO:
Bits [31 ..0]:   0011  0010  0000  0000  0001  1110  0000  1100

Bit 31:    0   RESERVED
Bit 30:    0   CFGBVS PIN
Bit 29:    1   BAD PACKET ERROR
Bit 28:    1   PUDC_B PIN
Bit 27:    0   HMAC ERROR
Bit 26:    0   CFG BUS WIDTH DETECTION
Bit 25:    1   CFG BUS WIDTH DETECTION
Bit 24:    0   RESERVED
Bit 23:    0   RESERVED
Bit 22:    0   RESERVED
Bit 21:    0   RESERVED
Bit 20:    0   CFG STARTUP STATE MACHINE PHASE
Bit 19:    0   CFG STARTUP STATE MACHINE PHASE
Bit 18:    0   CFG STARTUP STATE MACHINE PHASE
Bit 17:    0   SYSTEM MONITOR OVER-TEMP ALARM STATUS
Bit 16:    0   SECURITY ERROR
Bit 15:    0   IDCODE ERROR
Bit 14:    0   DONE PIN
Bit 13:    0   DONE INTERNAL SIGNAL STATUS
Bit 12:    1   INIT_B PIN
Bit 11:    1   INIT_B INTERNAL SIGNAL STATUS
Bit 10:    1   MODE PIN M[2]
Bit  9:    1   MODE PIN M[1]
Bit  8:    0   MODE PIN M[0]
Bit  7:    0   GHIGH STATUS
Bit  6:    0   GWE STATUS
Bit  5:    0   GTS_CFG_B STATUS
Bit  4:    0   END OF STARTUP (EOS) STATUS
Bit  3:    1   DCI MATCH STATUS
Bit  2:    1   PLL LOCK STATUS
Bit  1:    0   DECRYPTOR ENABLE
Bit  0:    0   CRC ERROR

COMMAND: show_idcode 0
INFO: IDCODE for device 0 -  13631093

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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Hi @linxinye1

From your inputs, I see Bit 29 is HIGH (BAD PACKET ERROR). It means configuration packets are corrupted.

Check for signal integrity, improper connections, or sudden power drop.

Does mcs created from single bit file get FPGA configured correctly?

At what CCLK frequency you are configuring FPGA?

Is it possible for you to share configuration schematic of your board?

Regards,
Bhushan

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Visitor linxinye1
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Registered: ‎07-29-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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       I use the SMC controller to write the data bus of FPGA, ARM is SAM5D27. And the FPGA's CCLK is connected to the ARM SMC's NWE signal,only there are datas the NWE can pull down.

     In the bootlader, I configured the SMC controller, then the FPGA's initialization, then write the configuration data. 

the initialization just as the continuous 8 selectMAP DATA Loading. the connection between ARM and FPGA as the picture.

Can you send a email to my email, it's hard to give you the picture and files. (zhao_liu@huacenav.com)

 (     In the Debug mode, After configuring the pins of FPGA, I tested writing data to the FPGA by ARM's SMC program, it's ok. )

1.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

回复: MultiBoot with 7 Series FPGAs Configuration

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Hello @linxinye1

Adding few updates (Sent on email) to this thread which can help others  ::::::::::::::::::::::::::::::::: 

GHIGH STATUS  goes high, indicates the configuration data has been loaded into the device ?

COMMAND: show_config_status 0

INFO:

Bits [31 ..0]:   0001  0010  0000  0000  0001  1110  1000  1100

 

Bit 31: 0   RESERVED

Bit 30: 0   CFGBVS PIN

Bit 29: 0   BAD PACKET ERROR

Bit 28: 1   PUDC_B PIN

Bit 27: 0   HMAC ERROR

Bit 26: 0   CFG BUS WIDTH DETECTION

Bit 25: 1   CFG BUS WIDTH DETECTION

Bit 24: 0   RESERVED

Bit 23: 0   RESERVED

Bit 22: 0   RESERVED

Bit 21: 0   RESERVED

Bit 20: 0   CFG STARTUP STATE MACHINE PHASE

Bit 19: 0   CFG STARTUP STATE MACHINE PHASE

Bit 18: 0   CFG STARTUP STATE MACHINE PHASE

Bit 17: 0   SYSTEM MONITOR OVER-TEMP ALARM STATUS

Bit 16: 0   SECURITY ERROR

Bit 15: 0   IDCODE ERROR

Bit 14: 0   DONE PIN

Bit 13: 0   DONE INTERNAL SIGNAL STATUS

Bit 12: 1   INIT_B PIN

Bit 11: 1   INIT_B INTERNAL SIGNAL STATUS

Bit 10: 1   MODE PIN M[2]

Bit  9: 1   MODE PIN M[1]

Bit  8: 0   MODE PIN M[0]

Bit  7: 1   GHIGH STATUS

Bit  6: 0   GWE STATUS

Bit  5: 0   GTS_CFG_B STATUS

Bit  4: 0   END OF STARTUP (EOS) STATUS

Bit  3: 1   DCI MATCH STATUS

Bit  2: 1   PLL LOCK STATUS

Bit  1: 0   DECRYPTOR ENABLE

Bit  0: 0   CRC ERROR

GHIGH signal  HIGH that signifies configuration data has been loaded and interconnects are activated. Kindly follow instruction provided in special startup condition Special Start-Up Conditions (Page 4).

For more details on configuration process check UG470 (v1.13.1) (Page 84 ~92 and Page 114).

Problem resolved, the last step start-up sequence, the bitstream generated by the ISE, the configuration parameters should be chose "CCLK"

Not "JTAG   CCLK",  I think , at the start-up stage, the FPGA's CCLK signal is provided by the ARM, not the  "JTAG   CCLK".

startup options issue.jpg

 

 

Regards,
Bhushan

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