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Visitor lvaldivia
Visitor
81 Views
Registered: ‎01-30-2019

Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

Hi

 

I Need help programming TWO spartanjtag chain.jpgJTAG chainschematic.jpgMy schematicxilinx diagram.jpgXilinx diagram 6 FPGAs with ONE xilinx XCF32P Prom. I looked around  UG380 and followed the diagram in chapter 9 (Master serial configuration) . I was able to generate a .MCS file and add 2 .BIT files to the prom file. After i upload the prom file to the XCF32P, i can see the desired output come from the first FPGA but not the second FPGA.

 

I am uploading a bit file that takes in a 100MHz clk signal at GCLK0 of the FPGA and outputs the signal out of some pin on the FPGA. The code is identical so there is no mix up in pins since each FPGA has its own connector for the output signal to be read. I was able to see the signal from both FPGAs when i upload the files directly through JTAG.

I read in UG380 that you can specify the bitstream for each device but i have not seen that option in impact. How would either prom know what file to upload? i dont remember setting that and i dont think there are examples of this.

 

let me know if it would be helpful to show scope plots of any pins.

I attached pictures of my schematic, the xilinx wiring diagram from UG380, and a picture of my jtag chain.

 

Below is the device status of both FPGAs

Thanks!

 

FPGA 1 (MAIN)

 


INFO:iMPACT - Current time: 1/31/2019 11:03:27 AM
// *** BATCH CMD : ReadStatusRegister -p 2
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'2': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         1
[10] MODE PIN M[1]                                                         :         0
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

FPGA 2 (SUPPORT)


INFO:iMPACT - Current time: 1/31/2019 11:08:21 AM
// *** BATCH CMD : ReadStatusRegister -p 3
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'3': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'3': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         1
[10] MODE PIN M[1]                                                         :         1
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

 

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1 Reply
Moderator
Moderator
49 Views
Registered: ‎01-15-2008

Re: Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

can you check the following which is pointed in ug380 in page 151

https://www.xilinx.com/support/documentation/user_guides/ug380.pdf

 

1) in the bitgen settings

DriveDone is disabled (all devices except the first)

DriveDone is enabled (first device)

 

2) done pins have 330 ohm pull-up resistors

3) you may try to setup BitGen DonePipe option in the bitgen

 

--Krishna

 

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