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Visitor lvaldivia
Visitor
184 Views
Registered: ‎01-30-2019

Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

Hi

 

I Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom. I looked around  UG380 and followed the diagram in chapter 9 (Master serial configuration) . I was able to generate a .MCS file and add 2 .BIT files to the prom file. After i upload the prom file to the XCF32P, i can see the desired output come from the first FPGA but not the second FPGA.

 

I am uploading a bit file that takes in a 100MHz clk signal at GCLK0 of the FPGA and outputs the signal out of some pin on the FPGA. The code is identical so there is no mix up in pins since each FPGA has its own connector for the output signal to be read. I was able to see the signal from both FPGAs when i upload the files directly through JTAG.

I read in UG380 that you can specify the bitstream for each device but i have not seen that option in impact. How would either prom know what file to upload? i dont remember setting that and i dont think there are examples of this.

 

let me know if it would be helpful to show scope plots of any pins.

I attached pictures of my schematic, the xilinx wiring diagram from UG380, and a picture of my jtag chain.

 

Below is the device status of both FPGAs

Thanks!

 

FPGA 1 (MAIN)

 


INFO:iMPACT - Current time: 1/31/2019 11:03:27 AM
// *** BATCH CMD : ReadStatusRegister -p 2
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'2': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         1
[10] MODE PIN M[1]                                                         :         0
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

FPGA 2 (SUPPORT)


INFO:iMPACT - Current time: 1/31/2019 11:08:21 AM
// *** BATCH CMD : ReadStatusRegister -p 3
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'3': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'3': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         1
[10] MODE PIN M[1]                                                         :         1
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

 

 

xilinx diagram.jpg

 

schematic.jpg

 

 

jtag chain.jpg

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5 Replies
Xilinx Employee
Xilinx Employee
158 Views
Registered: ‎06-21-2018

Re: Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

Hi lvaldivia,

Your schematic looks different than the one on UG380. Your schematic seems to have:

- Pull Up on PROG_B

- No Pull Up on DONE of the 2nd FPGA

- The DONE of the 1st FPGA disconnected

Is that your latest version of the schematic?

Thanks,

Andres

 

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Visitor lvaldivia
Visitor
115 Views
Registered: ‎01-30-2019

Re: Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

Thanks for your reply

 

Yes i disconnected the Done pin because neither FPGA was being programmed. i read the XCF32P data sheet and it mentions a standby state when the /CE enable pin is set high.

 

The fpga datasheet says the done pin should be pulled high, but the prom datasheet says it shouldnt be pulled high because it will put the prom in standby mode. I didnt know who to listen to.

 

The program is pulled high because the prom mentions CF should be pull high.

 

again, i dont know who to listen to, the prom and FPGA seem to contradict eachother.

 

Thanks!

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Xilinx Employee
Xilinx Employee
99 Views
Registered: ‎06-21-2018

Re: Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

Hi lvaldivia,

I recommend to follow the instructions of pages 149 - 151 of UG380.

Even the basic Master Serial Configuration diagram of page 26 handles the signals in a similar fashion.

Thanks,

Andres

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Visitor lvaldivia
Visitor
83 Views
Registered: ‎01-30-2019

Re: Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

Is there any user guide on this type of application? i was hoping to find some kind of example of 2 FPGAs and 1 Prom to use a baseline for my troubleshooting. UG380 mentions the configuration but it does not go into detail on how to actually program it.

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Moderator
Moderator
26 Views
Registered: ‎06-05-2013

Re: Need help programming TWO spartan 6 FPGAs with ONE xilinx XCF32P Prom

can you share the command which you are using for generating the bin file?
If possible try to use the command:

promgen -w -p mcs -c FF -o output_file -bpi_dc parallel -u 0 device1.bit downstream_device_2.bit

Thanks
Harshit
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