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Visitor aniltirli
Visitor
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Registered: ‎12-23-2018

Partial Reconfiguration

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Hi,

If i create two or more partial reconfigurable block in the floorplanning in Vivado with same physical size and including same FPGA resources. Will the generated bit files describe the two regions in the same way? Can i load the same configuration to the two partial regions even if a configuration synthesised and implemented for one region in Vivado ?

Thanks in advance,

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Partial Reconfiguration

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No you cannot do this.

The two regions actually have different coordinates, and the partial bitstreams generated will identify the coordinates.

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Xilinx Employee
Xilinx Employee
439 Views
Registered: ‎08-10-2008

回复: Partial Reconfiguration

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No you cannot do this.

The two regions actually have different coordinates, and the partial bitstreams generated will identify the coordinates.

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Don't forget to reply, kudo, and accept as solution.
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140 Views
Registered: ‎05-17-2018

回复: Partial Reconfiguration

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To be sure I understood the answer, it means that the partial binary is generated for the couple "Reconfigurable Module + Reconfigurable partition" and if  a Reconfigurable Module can be placed in multiple Reconfigurable Partitions we will have for this unique Reconfigurable Module multiple partial binaries?

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-17-2008

回复: Partial Reconfiguration

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Yes, exactly. Even though the function of the module is logically identical, the physical implementation, both of the module in a unique location as well as the static design that surrounds it, will be completely unique. A unique bitstream for this unique location is required. Partial bitstreams are not relocatable.
thanks,
david.