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Voyager
Voyager
639 Views
Registered: ‎08-16-2018

Problem rebuilding AC701 Multiboot Design

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I took the XTP226 and its associated files as a starting point to develop a multiboot feature in Artix-7.

When flashing the already built files, it works fine. 

But if I run the implementation from the source files, it doesn't.... sometimes (I fiddled with a number of possibilities) the INIT led remains red (on the AC701 board), others the DONE led doesn't come on.

I have to say I'm using Vivado 2017.2 while the example design were done on 2015.1. Yes, I upgraded all the IPs.

 

The configuration I'm using for the golden fw is:

set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUS_WIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 32'h00400000 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

And the same for the upgrade, except the  BITSTREAM.CONFIG.NEXT_CONFIG_ADDR  that is taken off.

 

I went a step back and did a simpler design with just a Verilog file dividing the clock and scrolling the Leds. Built two versions scrolling in different directions and flashed them as a 'golden' and 'upgrade' and it worked. So I'm confident the configuration for multiboot is right. 

I suppose the microblaze does something extra. I know it reads the switches and writes the HWICAP to reboot different configurations, but in any case I would expect a fallback to the golden fw.

 

Any pointers?

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Voyager
Voyager
544 Views
Registered: ‎08-16-2018

Re: Problem rebuilding AC701 Multiboot Design

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I guess something in the block design went wrong when working from scratch in Vivado 2017.2. I built it, then modified and built again, probably something got screwed up. I re-did it again without building until finished and it worked.

I got that message about "IPs are locked" but not even the 'reset_project' TCL command fixed it, and the subsequent working project also has that warning. Weird...

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Xilinx Employee
Xilinx Employee
626 Views
Registered: ‎11-30-2007

Re: Problem rebuilding AC701 Multiboot Design

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Do you have a state machine in each of your multiboot designs that controls the ICAPE2 interface when a multiboot trigger is issued?  The state machine should issue the IPROG command via ICAPE2 as shown in UG470 Table 7-1:

 

20180907_MultiBoot_1.png

 

You can reference the Forum Post below for more details:

 

https://forums.xilinx.com/t5/Configuration/Exchange-mcs-file-while-running-fpga/m-p/881490#M9527

 

Thank you.

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Moderator
Moderator
609 Views
Registered: ‎06-05-2013

Re: Problem rebuilding AC701 Multiboot Design

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Have you tried to load the bit file first? If that works or not. Golden and update image works then we expect the mcs file to work. Are there any warnings when you upgraded the design from 2015.2 example design to 2017.2 design.

If you can share the design properties and status registers then we can check them.

Open implemented design,run the below command
report_property -all [current_design]

And status registers from Vivado HW manager.

Thanks
Harshit
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Voyager
Voyager
545 Views
Registered: ‎08-16-2018

Re: Problem rebuilding AC701 Multiboot Design

Jump to solution

I guess something in the block design went wrong when working from scratch in Vivado 2017.2. I built it, then modified and built again, probably something got screwed up. I re-did it again without building until finished and it worked.

I got that message about "IPs are locked" but not even the 'reset_project' TCL command fixed it, and the subsequent working project also has that warning. Weird...

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Moderator
Moderator
537 Views
Registered: ‎06-05-2013

Re: Problem rebuilding AC701 Multiboot Design

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IPs are locked because the version of IPs gets updated from one release to another. You can do a report_ip_status and then update the IPs using upgrade_ip [gets_ips]

Let us know if multiboot example is not working. I can try to update the the same.

Thanks
Harshit
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