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Adventurer
Adventurer
7,247 Views
Registered: ‎09-27-2010

Problems with configuration of 4x SPI after using Vivado

Hello.

I have a device with two xc7a200tfbg676. Each has it's own 4xSPI flash (N25Q128A).

Initally I worked using ISE 14.5 and everything was good, but then I switched to Vivado2014.4 in order to have access to Aurora core without bugs.

I have programmed flash by hardware manager but new cofiguration doesn't seem working very well, so I am trying to reprogram old configuration back using iMPACT but now programming fails.

I've tried to program another device with Vivado and then again with iMPACT and I've got the same error.

Is Vivado breaks something in FPGA? What's going on?

 

Error message:

INFO:iMPACT - Current time: 08.07.2015 15:10:56
// *** BATCH CMD : Program -p 1 -dataWidth 4 -spionly -e -v -loadfpga
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading:   38.56 C, Min. Reading:   36.10 C, Max. Reading:   40.53 C
1: VCCINT Supply: Current Reading:   1.040 V, Min. Reading:   1.037 V, Max. Reading:   1.040 V
1: VCCAUX Supply: Current Reading:   1.790 V, Min. Reading:   1.787 V, Max. Reading:   1.793 V
2: Device Temperature: Current Reading:   39.55 C, Min. Reading:   35.61 C, Max. Reading:   39.55 C
2: VCCINT Supply: Current Reading:   1.040 V, Min. Reading:   1.037 V, Max. Reading:   1.046 V
2: VCCAUX Supply: Current Reading:   1.793 V, Min. Reading:   1.790 V, Max. Reading:   1.796 V
Unprotect sectors: FALSE
ERROR:iMPACT - XSDB Master timed out.
SPI core is not found in XSDB.
Found Slave on Bus Index.
Found Slave on Bus Index.
SPI core clock speed value = 0xA801.
key: period_frc, value: 0
key: dclk_has_reset, value: 0
key: period_int, value: 10
Found Slave on Bus Index.
Found Slave on Bus Index.
SPI core clock speed value = 0xA801.
PROGRESS_START - Starting Operation.
ERROR:Cse - Error writing to Core controller.
ERROR:Cse - Error writing to Core controller.
'1': IDCODE is 'ffffff' (in hex).
'1': ID Check failed.
INFO:Cse - The operation did not complete successfully.
'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
PROGRESS_END - End Operation.
Elapsed time =      8 sec.

Ilya
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Adventurer
Adventurer
7,234 Views
Registered: ‎09-27-2010

Re: Problems with configuration of 4x SPI after using Vivado

If it's important, when I used Vivado, the problem was that the hardware manager couldn't find any debug cores despite I had inserted them.

Ilya
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