08-11-2019 10:02 AM
I'm using a Kintex-7 to program another Kintex-7. The FPGA is set up as a slave select map x32 and it's being programed by another FPGA which through PCIE. The software graps bitstream file and send through PCIE and I wrote logic that handles the programming (done,init_B,csi_b,rdwr_b,data,cclk). The bitstream file is being send to me and I just toggle csi_B until Done is high (non-continous). I have several questions.
1) I program FPGA2 by toggle csi_b until Done line is high. I noticed that when the Done is high, the FPGA is partial configured. At the same time, I still have bitstream data and if I don't write all data then my FPGA is not fully programmed. When the Done line is high, I continue to write data for another 4us until there's no more bitstream data then my FPGA is fully configured. Based on the FPGA Configuration (UG), when the Done line is high the FPGA is configured and write is ignored. How come in my case If want to fully programm the FPGA I have to continue writing data even when Done is high?
2) I have one bitstream file and programmed successfully everytime. Also, I have tried it on mutiple boards and programmed successfully. I have issue when I tried another bitstream file (different design), the Done line never go high. I have tried it on multiple boards and Done line never go high. I verify the design setup in Vivado 2018.2 to make sure it target the right device and everything looks good. I also take that same bitstream file and programmed by JTAG and the Done line goes high. Is there a way in JTAG that you can look at the Register to verify how many Word (32-bit) left before Done line goes high? Is the Bit Generator caused the file not to program? Can the design caused the Done not to go high?
08-13-2019 02:58 PM
08-12-2019 07:35 PM
1. Expected. All Xilinx FPGAs, after you send out all the 'valid' config data into FPGA, DONE would pull up high at startup phase 4 by default, but FPGA still need some extra clock cycles to initialize itself. Usually, send out the complete bitstream will finish this work. Open it in UE, you can see FFs or 20 00s at the end of file, these are for the 'extra' cycles.
2. The second bitsteam does not have byte swap, this is the most possible reason. Check UG470 for 'bit or byte swap' for more details.
If not, read out the Device Status reg and let us help you.
08-13-2019 01:43 PM
08-13-2019 01:56 PM
Can you try to use bin file(atleast header would be out) and add a padding before the sync word. Where you have added those 0's or 1's?
Refer to the below snapshot, try before sync word.
08-13-2019 02:55 PM
Rather start out programming with everything (include headers,sync word), can you just start out with Sync Word? or FPGA needs some headers before Sync Wordz?. If we start out with Sync Word first to the end of the file, then the file size is equal to multiple of 4 bytes. I added 0's or 1's at the end of the file.
08-13-2019 02:58 PM
08-15-2019 06:35 AM
From the sync word, I have to go back to where all FF's begin and it's working. Like you said before, using BIN file will fix this issue as well since BIN file is fixed. Thank very much for your help.