05-23-2019 10:50 AM
I am currently using an Artix-7 XC7A200T and trying to add the Soft Error Mitigation core to the design. This design already has Partial Reconfiguration set up within it. After generating the core and adding it to my top-level entity, I generated the bitstream and connected to the monitor interface via Tera Term. I received the following on the display:
X7_SEM_V4_1 SC 01 FS 0B ICAP
From what I understand, the SEM has entered the initialization phase but cannot correctly interface with the ICAP ports and therefore never enters observation. I tried using the example design generated from the SEM core, I checked the ICAPE2 primitive in the example configuration file (sem_cfg.vhd), and I think the problem lies with the SEM and PR connections to the ICAP.
Where would I go within the PR design to find where it interfaces with the ICAP ports, and how could I best resolve the SEM/PR conflict?
05-23-2019 12:30 PM
PR and SEM IP was never considered. In fact the SEM IP assumes it 'owns' the ICAP, and once started, the CRAM will never intentionally be changed. If the bitstream changes, SEM IP must be completely restarted by a power cycle - no provision is made to reset or restart. This was a concious decision because such a feature would make the SEM vulnerable, reducing its effectiveness.
05-24-2019 09:43 AM
Above outcome of SEM IP show clocking issues. If you refer to https://www.xilinx.com/support/documentation/ip_documentation/sem/v4_1/pg036_sem.pdf (Page#119-120) you will find the debugging tips. Below is the snapshot of same.