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Visitor kuldeepsi
Visitor
334 Views
Registered: ‎04-04-2019

SPI Configuration and Flash Programming in UltraScale FPGAs.

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Hi,

I have a SPI NOR flash memory attached to the Xilinx ultrascale FPGA "KU060" on a custom board. 

Sometimes the FPGA controller is unable to fetch the golden image (there is no image present in the work sector). Basically it is showing a build to build variation. Builds made from the same location have failed as well as passed in fetching the golden image.

Tool used - Vivado 2017.2

Bitsteam settings used in the golden image -

set_property BITSTREAM.CONFIG.CONFIGRATE 90 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]

set_property BITSTREAM.CONFIG.TIMER_CFG 0xF7FD23 [current_design]

set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]

set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x02000000 [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]

What is the expected behaviour if no work image is present and the FPGA controller jumps to the work sector ?

What is the expected behaviour of the watchdog counter? What is the frequency at which watchdog counter is expected to operate ?

 

 

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Xilinx Employee
Xilinx Employee
210 Views
Registered: ‎01-10-2012

Re: SPI Configuration and Flash Programming in UltraScale FPGAs.

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@kuldeepsi 

Glad you have your constraints sorted out !

On the Watchdog timer, it runs on CCLK as mentioned on the UG570  during configuration.So, when you jump to your 2nd image the CCLK is set to default 3Mhz and the watchdog would run based on this,since you dont have a valid image the TIMER will timeout when it has counted till the set value i.e 0xf7fd23 which is approx 6 sec, and thats what you are seeing in your H/W.

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Xilinx Employee
Xilinx Employee
285 Views
Registered: ‎01-10-2012

Re: SPI Configuration and Flash Programming in UltraScale FPGAs.

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@kuldeepsi 

>Builds made from the same location have failed as well as passed in fetching the golden image.

Can you please elaborate this ?

Are you sure the TIMER setting is appropriate ? Can you show the calculation how/why you arrived at the value.

Visitor kuldeepsi
Visitor
240 Views
Registered: ‎04-04-2019

Re: SPI Configuration and Flash Programming in UltraScale FPGAs.

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@gurupra 

So I was using the below command to enable watchdog counter -

set_property BITSTREAM.CONFIG.TIMER_CFG 0xF7FD23 [current_design] # 6 sec

A semicolon is missing before the # as per the command syntax, so the tool did not take this command, due to which the watchdog counter was disabled and the fallback to golden image did not happen.

Earlier I had used the same command without comment in the same line, which followed the command syntax and the watchdog counter was enabled, which let the controller to fallback to golden image.

> Are you sure the TIMER setting is appropriate ? Can you show the calculation how/why you arrived at the value.

Yes, the TIMER setting is proper. I arrived at the mentioned watchdog counter value based on trial, calculating the time taken on the board.

The application note "xapp1257-multiboot-fallback-spi-flash" mentions the watchdog timer period to be 5120 ns.

Theoretically the timer value calculated for watchdog timer with value 0xf7fd23 is ~83 sec.

But on board the time taken by the controller to fallback to golden image is ~6 sec.

The watchdog timer period seems to differ from the value mentioned in the application note.

Please specify the working of watchdog counter. What is the frequency at which it is expected to work ?

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
211 Views
Registered: ‎01-10-2012

Re: SPI Configuration and Flash Programming in UltraScale FPGAs.

Jump to solution

@kuldeepsi 

Glad you have your constraints sorted out !

On the Watchdog timer, it runs on CCLK as mentioned on the UG570  during configuration.So, when you jump to your 2nd image the CCLK is set to default 3Mhz and the watchdog would run based on this,since you dont have a valid image the TIMER will timeout when it has counted till the set value i.e 0xf7fd23 which is approx 6 sec, and thats what you are seeing in your H/W.