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Newbie clim
Registered: ‎04-06-2016

Slave Serial Daisy Chain Virtex 5

Dear Experts,


I have a board that has two V5s in a serial daisy chain as configured in UG191 Figure 2-4. I would like to use a CPU to program both FPGAs. Initally the upstream board was put into Master Serial (M[2:0]=0) but since the CPU is the one providing the config clock, I cut the traces and according to the V5 datasheet, M[2:0] is pulled up internally putting the V5 into Slave Serial mode. I confirmed that the V5 is in Slave Serial mode by reading the configuration register over JTAG using Chipscope:



Bit 31:    0    
Bit 30:    0   RBCRC_ERROR
Bit 29:    0   IPROG_EVENT
Bit 28:    0   WRAP_ERROR
Bit 27:    0    
Bit 26:    0   BUS_WIDTH
Bit 25:    0   BUS_WIDTH
Bit 24:    1   FS
Bit 23:    1   FS
Bit 22:    1   FS
Bit 21:    0    
Bit 20:    0   STARTUP_STATE
Bit 19:    0   STARTUP_STATE
Bit 18:    0   STARTUP_STATE
Bit 17:    0    
Bit 16:    0   DEC_ERROR
Bit 15:    0   ID_ERROR
Bit 14:    0   DONE
Bit 13:    0   RELEASE_DONE
Bit 12:    1   INIT_B
Bit 11:    1   INIT_COMPLETE
Bit 10:    1   MODE M2
Bit  9:    1   MODE M1
Bit  8:    1   MODE M0
Bit  7:    0   GHIGH_B
Bit  6:    0   GWE
Bit  5:    0   GTS_CFG_B
Bit  4:    0   EOS
Bit  3:    1   DCI_MATCH
Bit  2:    1   DCM_LOCK
Bit  1:    0   PART_SECURED
Bit  0:    0   CRC_ERROR



I then generated a binary file using iMPACT. I selected the BPI Flash -> Configure Single FPGA -> V5 -> 64M -> BIN (Swap Bits Off). My CPU already swap bytes so I do not need that option when creating the binary file.


I then added my two bit files in the order of the daisy chain meaning upstream FPGA first then downstream FPGA second. I tried using the binary file generated but the configuration did not work. When FPGAs are not configured, the board current is at 1.86A, but when I attempt to program, the current does up to 1.88A; I suspect the board was partially configured.


I scoped DIN, PROG, INIT, and CCLK, and nothing looks abnormal; in fact we use the same code to program another board that only has a single V5 and that works. When I scoped DOUT, I noticed that the V5 was output a constant high and no data is passed to the downstream FPGA.


How do I get the upstream V5 to pass configuration data to the downstream V5?



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