10-18-2018 01:29 AM
10-18-2018 01:41 AM
Can I clarify please,
Do you mean the fpga as slave or master ?
if its mater, it will try to read the flash at start up,
if slave the fpga will wait to be written to,
10-18-2018 01:50 AM - edited 10-18-2018 01:51 AM
I mean FPGA in Master SPI mode, so I understand it will start configuration after power-on or when PROGRAM_B is driven low. So it seems that my connection needs 6 lines: MOSI, DIN, CCLK , CSO_B, DONE and PROGRAM_B. I'm not sure about INIT_B.
I understand there is no Slave SPI mode.
10-18-2018 01:57 AM
10-18-2018 02:16 AM