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Spartan 6 mode pins pull up and down values

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Adventurer
Posts: 95
Registered: ‎09-08-2009
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Spartan 6 mode pins pull up and down values

 

 

Dear Gurus,

 

I have been searching the documentation for Spartan 6 to find the best resistor values for M0 and M1

I found two different sources, one documentation and one reference design.

Should I connect directly (to GND or VCC) or via 200R or 2.4K R

source1.png
source2.png

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Newbie
Posts: 1
Registered: ‎08-12-2017

Re: Spartan 6 mode pins pull up and down values

Whether or not to even use resistors, what values to use, or just tie M{1:0]
to Vccio/GND depends on the answers to at least these questions:

1. Do you need flexibility to change what config. mode to use?

1a. If yes, then what kind of flexibility - manual (ie., DIP switches, PCB
version, etc.), or controlled by some other device?

2. Do you need to use the M[1:0] pins as IOs after configuration?

2a. If yes, what conditions apply to the mode signals as a result of
externally connected circuitry during FPGA config.?

3. What IO standard will be used on the mode pins?


I have a Spartan-6 design with the chip connected to a TI TMS320F2812 external
memory interface (XINTF) where two of the F2812's data bus bits (XDn) are
shared with the FPGA's M[1:0] pins. I'm using "Master Serial/SPI" mode, so I
want the mode bits to be M[1:0]=01b during configuration, and controlled by
the F2812 afterwards.


The M[1:0] pins have default pullups with strength of 250-500µA, and my
connected device also has pullups on its XDn signals when inactive, with about
140µA. Thus, there may be up to 640µA of pullup current sourced from +3.3V
on the mode nets during the config. phase.


The key then is to ensure that (with IOSTANDARD = LVCMOS33), M1 stays low
(<0.8V) during config. despite the influence of the combined (but relatively
weak) pullups. It must also be able to be driven high (>2.0V) by the 'F2812's
data bus drivers, post-config.


I chose a 820 ohm resistor to GND for M1, and a (somewhat superfluous, "just
pick something") 18k PU to +3V3 on M0. A 1k pulldown on M1 would probably
have been Ok, too.


Thus, the max. voltage on M1will be 0.55V (if 5% tol. R). This provides 0.25V
of noise margin. I like to have a min. of 0.2V noise margin for low values,
preferably 0.4V.


Also when the 'F2812 drives the M1 IO pin high after config., it's 4mA drive
strength will be able to produce Vih≥3.1V, which is plenty of noise margin.


I don't need the ability to change config. modes, but I still left open the
possibility of using a different mode by implementing the PU/PD resistors
using a SMD footprint with 3 pads. The center one is the signal, one side
goes to +3.3V, the other side to GND. The placement of the resistor is fixed
in the PCB design. But for a different PCB rev., I could move the resistors
to the other positions. Simply providing two ordinary resistor placements,
with one populated and the other empty, would also suffice to provide this
sort of flexibility.


These are the sorts of considerations one must deliberate about in order to
decide how to deal with the mode pins.


Have fun!

View solution in original post


All Replies
Moderator
Posts: 2,049
Registered: ‎08-01-2012

Re: Spartan 6 mode pins pull up and down values

The M1 and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors (2.4 kΩ), or tied directly to ground or VCCO_2.

 

Please refer http://www.xilinx.com/support/documentation/user_guides/ug380.pdf for more details

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Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

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Newbie
Posts: 1
Registered: ‎08-12-2017

Re: Spartan 6 mode pins pull up and down values

Whether or not to even use resistors, what values to use, or just tie M{1:0]
to Vccio/GND depends on the answers to at least these questions:

1. Do you need flexibility to change what config. mode to use?

1a. If yes, then what kind of flexibility - manual (ie., DIP switches, PCB
version, etc.), or controlled by some other device?

2. Do you need to use the M[1:0] pins as IOs after configuration?

2a. If yes, what conditions apply to the mode signals as a result of
externally connected circuitry during FPGA config.?

3. What IO standard will be used on the mode pins?


I have a Spartan-6 design with the chip connected to a TI TMS320F2812 external
memory interface (XINTF) where two of the F2812's data bus bits (XDn) are
shared with the FPGA's M[1:0] pins. I'm using "Master Serial/SPI" mode, so I
want the mode bits to be M[1:0]=01b during configuration, and controlled by
the F2812 afterwards.


The M[1:0] pins have default pullups with strength of 250-500µA, and my
connected device also has pullups on its XDn signals when inactive, with about
140µA. Thus, there may be up to 640µA of pullup current sourced from +3.3V
on the mode nets during the config. phase.


The key then is to ensure that (with IOSTANDARD = LVCMOS33), M1 stays low
(<0.8V) during config. despite the influence of the combined (but relatively
weak) pullups. It must also be able to be driven high (>2.0V) by the 'F2812's
data bus drivers, post-config.


I chose a 820 ohm resistor to GND for M1, and a (somewhat superfluous, "just
pick something") 18k PU to +3V3 on M0. A 1k pulldown on M1 would probably
have been Ok, too.


Thus, the max. voltage on M1will be 0.55V (if 5% tol. R). This provides 0.25V
of noise margin. I like to have a min. of 0.2V noise margin for low values,
preferably 0.4V.


Also when the 'F2812 drives the M1 IO pin high after config., it's 4mA drive
strength will be able to produce Vih≥3.1V, which is plenty of noise margin.


I don't need the ability to change config. modes, but I still left open the
possibility of using a different mode by implementing the PU/PD resistors
using a SMD footprint with 3 pads. The center one is the signal, one side
goes to +3.3V, the other side to GND. The placement of the resistor is fixed
in the PCB design. But for a different PCB rev., I could move the resistors
to the other positions. Simply providing two ordinary resistor placements,
with one populated and the other empty, would also suffice to provide this
sort of flexibility.


These are the sorts of considerations one must deliberate about in order to
decide how to deal with the mode pins.


Have fun!