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612 Views
Registered: ‎11-27-2017

Time override

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Hi,

in the ds892 document for Ultrascale family FPGA, two different ranges of time programming override are defined, showed in the image attached. It shows the case of a long ramp rate time (40ms) with POR pin tied to GND, or short ramp rate time (2ms) with POR override activated (tied to VCCINT). However, the case of short ramp rate (2-10ms) with POR function disabled (tied to GND) is not considered. What will the range of POR time be? Can the minimum value be 0ms?

Thank you very much!

Captura de pantalla 2018-11-20 a las 11.27.49.png

 

 

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Community Manager
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Registered: ‎07-23-2015

Re: Time override

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ammantas@iaa.es 



As FPGA configuration bank supply and flash memory supply are the same, then TPOR timer will start at VCC=1.7V, and as in the TPOR specification for slow ramp rates, TPOR can be 0ms, in this case, our flash memory will not be yet ready, and programming can fail.

Since you are sharing the same supply of VCCO_0 and the SPI flash VCC, I would recommend holding the FPGA INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure and release to High after the flash becomes ready.

Do make sure to go through the Power-On Sequence Precautions for Flash section from Page#40 of UG570 v1.9.1 

- Giri
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Community Manager
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Registered: ‎07-23-2015

Re: Time override

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ammantas@iaa.es 

To clairfy, the POR_OVERRIDE pin was added from Ultrascale family to reduce the TPOR delay if user has a faster ramp rate of power supplies. So, if you have faster ramp rates (2ms as mentioned in datasheet), you need to enable the POR_OVERRIDE by tying it to VCCINT to reduce the TPOR delay. If you have slower ramp rates, you disable the POR_OVERRIDE by tying it to GND and having the TPOR delay as specified in datasheet. 


 

  However, the case of short ramp rate (2-10ms) with POR function disabled (tied to GND) is not considered.

Because you either have fast ramp times (POR_OVERRIDE = 1) or slow ramp times (POR_OVERRIDE = 0). Based on these settings, you will have the Min/Max TPOR specified in Datasheet. 

Quoting the function of POR_OVERRIDE and TPOR definition from UG570 for reference 

"The FPGA automatically provides a delay between power-on and the beginning of configuration, called the power-on reset (POR) delay. The TPOR delay starts from the time the last required supply rail is supplied to the FPGA at 95% of its nominal value, and ends with the FPGA asserting the INIT_B pin, sampling the Mode pins, and starting to toggle the CCLK if master mode is selected."

"The Power On Reset Override select (POR_OVERRIDE) pin must be set High or Low to determine the power-on delay before configuration begins. The POR_OVERRIDE is a logic input pin referenced between VCCINT and GND. When the POR_OVERRIDE pin is High at power-up (e.g., connected to the VCCINT supply rail), the POR delay is shortened as specified in the data sheet. When the POR_OVERRIDE pin is Low (e.g., connected to GND), the POR
delay is longer. POR_OVERRIDE should be connected to GND unless the flash will always be ready as soon as the FPGA is powered up"

- Giri
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567 Views
Registered: ‎11-27-2017

Re: Time override

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Dear gnarahar,

thank you very much for your answer. My question is more related with slow ramp rates. With the configuration bank supply as the last ramp  (VCC_0 = 1.8V), the Tpor timer starts at 95% of this voltage (1.71V), which is the same than most of the SPI flash memories recommended for Kintex Ultrascale. In our case, we use MT25QU512ABB8ESF-0SIT, which needs around 300us from VCC=1.7V for be ready to be used by the FPGA. As FPGA configuration bank supply and flash memory supply are the same, then TPOR timer will start at VCC=1.7V, and as in the TPOR specification for slow ramp rates, TPOR can be 0ms, in this case, our flash memory will not be yet ready, and programming can fail.

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Community Manager
Community Manager
562 Views
Registered: ‎07-23-2015

Re: Time override

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ammantas@iaa.es 



As FPGA configuration bank supply and flash memory supply are the same, then TPOR timer will start at VCC=1.7V, and as in the TPOR specification for slow ramp rates, TPOR can be 0ms, in this case, our flash memory will not be yet ready, and programming can fail.

Since you are sharing the same supply of VCCO_0 and the SPI flash VCC, I would recommend holding the FPGA INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure and release to High after the flash becomes ready.

Do make sure to go through the Power-On Sequence Precautions for Flash section from Page#40 of UG570 v1.9.1 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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