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Visitor untilyou
Visitor
7,240 Views
Registered: ‎09-19-2014

Virtex-5 FPGA readback with icap

hi,

i am trying to implement readback ex with icap using virtex-5 fpga.by reading the ug191 doc, there are still some questions i do  not understand. now i list them as following:

1.The process for reading configuration memory from the FDRO register: 1st step,Write the Bus Width detection sequence and Synchronization word to the device.but what the device refered to? should i assign address when i write the data to the device?

 

2.How should I do to read data from FDRO reg?should i assign address when i read  data from it?

 

3.i  am a beginner, if you can send me some routine for reference, i will be much grateful to you .

 

Thanks,

Jianqiu Xu

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Xilinx Employee
Xilinx Employee
7,212 Views
Registered: ‎08-25-2010

Re: Virtex-5 FPGA readback with icap

Hi Jianqiu,

 

Please follow steps in table 7-2, ug191, just sending configuration data based on ICAP write/read timing. The configuration data, after referring to table 6-2/6-3/6-4, you should learn what that means.

 

Thanks

Simon

Thanks
Simon
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