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Visitor sukumar441
Visitor
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Registered: ‎09-03-2018

Virtex Ultrascale Plus (VU9P)::Programing QSPI's operating at different bank volatges connected through a level translator

Hi

In our design we connected 2 QSPI's 1 With Bank 0  which is operating at 1.8V and other to Bank 65 which is operating at 1.2 through level translator as shown in attached screen. While programming in x8 mode  during second QSPI erase and program operation failed. Please find the attached Error log and configuration window of vivado. Can you suggest us how to program two QSPI in x8 mode at the same time

QSPI block diagram.pngQSPI block diagramQSPI error log.pngVIVADO error logConfiguration settings.pngVivado config window

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Virtex Ultrascale Plus (VU9P)::Programing QSPI's operating at different bank volatges connected through a level translator

P37, UG570:

The interface pins associated with the configuration mode can span bank 0 and bank 65,
primarily when using 8-bit or wider data interfaces. When both banks are used for a
configuration interface, the V
CCO pins for both banks must receive the same voltage to
ensure a consistent I/O voltage interface and timing for all of the configuration interface
pins. Using the same voltage for banks 0 and 65 is recommended because it allows the
option of using an 8-bit or wider configuration mode, and avoids the I/O transition
described under
I/O Transition at the End of Startup, page 152.

 

 

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