05-16-2018 09:13 AM
The board I'm using has a buffered jumper to hold INIT_B low on power up and throughout JTAG boundary scan testing. I find if the XC7A50T transitions from EXTEST to TAPRESET, the FPGA configures itself from SPI flash. That was not the intent. I'm wondering how it could be doing this and if there is another pin the should have be held to disable configuration during all possibilities that can occur in JTAG boundary scan test, perhaps on the SPI flash itself.
05-16-2018 10:28 AM
what ever you do end up with
do not hold the prog_b pin low, as that asserts the fpga internal reset, which kills the jtag in the fpga.
gives all sorts of interesting readings...
init_b is the way I would do this also,
do you have a small enough pull up on init_b, so it goes cleanly up after jtag
One last thing,
in the jtag , I don't suppose the init_b can be driven ?
set it as an input in the jtag ( if you can ! )
05-16-2018 11:13 AM
Yes the init_b can be driven and was during EXTEST. I thought I got rid of that, but I will check again. A 5K pull up is there, but the buffered jumper (powered by the same voltage source as the pull up) should bring it low until someone manually removes the jumper. I also noticed from another post there is a default pull up on the init_b referring to UG908. I could keep init_b low at EXTEST to see what happens.