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6,883 Views
Registered: ‎05-01-2014

Yet Another Spartan 6 Done pin low

Hello all,

I apologize for the banality of the subject, but I need your help for solving this common issue.

I have read already many post, but unfortunately I wasn't lucky enough to found a solution.

 

I have a S6 LX75, I can configure with JTAG/Impactt without problem, but when I try to configure with Serial slave the done pin stays low. and I can't figure out what is going on.

 

 

1. I'm using ISE14.7

2. I'm generating an hex file using impact (with the start up option CCLK on)

3. I'm sending the hex file to a microcontroller wich generates the PROGRAM_B, CCLK + FPGA DIN signal ( I have checked these signals with an oscilloscope and they seems OK, for example I can see the first 16 "ff" followed by the synchronization word the CCLK is not continuous, but this should not be a problem on SLave serial mode, with an oscilloscope I have checked all the timing and the signal integrity for both CCLK and DIN and them both seems OK.

I have also created a dummy FPGA that sends the CCLK and DIN to an LED to see if the BGA was properly soldered and they seems connected correctly.

 

4. I drive Program_B low, wait Init_b goes low, then I drive Program_B high, and wait Init_b to go high

5. I wati 10 msec ( I have tried without any delay as well) and then I start program the FPGA

6.I have monitored the Init_B all the way from the beginning to the end and it goes down only when Program_b is low

7. I have tried to "corrupt the hex file at the beginning (just after the syncronization words" and strange enough I can't see INIT_B goes low???

 

8. with impact I have tryed to read the configuration register and I always read the same values:

INFO:iMPACT - Current time: 30/04/2014 22:10:25
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 0
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 1
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 0
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

 

 

I believe that for some reason the CCLK is ignored, otherwise when I corrupt  the hex file I should have see the INIT pin go low. Is that correct?

 

Is it possible that even if the CCLK option is on (from ISE) for some reason (a bug ot something) the CCLK is changed to JTACG? I remember this was the case on ISE 9.x (yes I'm so old)

 

Any help is really appriciated.

 

Best regards,

Francesco

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17 Replies
Instructor
Instructor
6,878 Views
Registered: ‎08-14-2007

Re: Yet Another Spartan 6 Done pin low

My first guess is that you have the bit order swapped.  i.e. the config file expects the MSB to go first but you're shifting LSB first (or vice-versa).  You can check the start of the .hex file for the sync code AA995566 or something like that.  See if it matches the binary file or .bit file which want MSB first.  If you use Impact to create a generic .hex file, I think the default is to swap bits, so your hex file would then have 5599AA66 or something like that.  Then you'd need to shift LSB first.

 

Note that the re-assertion of INIT_B will only happen after the part has detected the start of configuration by recognizing the startup sync code.

 

The only other possibility I can think of is that your mode pins are not set correctly for slave serial mode.  The status read back from the part looks pretty much like the FPGA never even got started configuring.

-- Gabor
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6,861 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

Hello gabor,

I agree with you, it looks like that I haven't even started to configure the FPGA.

 

I have verified and both M0 and M1 are high (this is also visible when I read the configuration register).

and the sync code starts with AA995566.

I write 10101010   10011001    01010101    0011 0011. (on the rising edge of the clock).

Do you know of any issues  when the CCLKC is non continuous clock on serial mode? 

 

If I stop the microcontroller to send data after I have just sent the configuration word and I then I try to read with IMPACT the configuration register what am I supposed to see?

 

Thanks,

Francesco

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Historian
Historian
6,852 Views
Registered: ‎02-25-2008

Re: Yet Another Spartan 6 Done pin low


@podericofrancesco wrote:

 

Do you know of any issues  when the CCLKC is non continuous clock on serial mode? 


Just a data point: I've done slave-serial configuration of a Virtex-4 by bitbanging from a micro. The CCLK in that case was not continuous 50% duty cycle and it worked fine.

----------------------------Yes, I do this for a living.
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Instructor
Instructor
6,850 Views
Registered: ‎08-14-2007

Re: Yet Another Spartan 6 Done pin low

"I write 10101010   10011001    01010101    0011 0011. (on the rising edge of the clock)."

 

The FPGA samples DIN/D0 on the rising clock edge.  So normally a micro would provide plenty of setup and hold time, usually by changing the data at the same time as driving the clock low.  As Bassman says, there should be no problem with slow or intermittent clocks as long as setup and hold time are maintained.

-- Gabor
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6,846 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

Hen I clock the data in the DO seems to be in Hi-Z.

it really looks like the FPGA doesn't know I'm trying to programming.

I'm puzzled!

 

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6,833 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

When HSWAPEN is LOW the FPGA doesn't seems to respond to Impact!

 

I don't think this is right! I believe it should still work am I missing something?

 

 

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Teacher eteam00
Teacher
6,829 Views
Registered: ‎07-21-2009

Re: Yet Another Spartan 6 Done pin low

I have used iMPACT successfully for many years with boards designed with HSWAPEN tied LOW.

 

-- Bob Elkind

SIGNATURE:
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6,807 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

I agree it should work, HSWAPEN when 0  enable a pullup on the suspend pin. butthe suspend pin is tied  to gnd with a 0 ohm resister therefore it should work.

I cal also see less current (drained from the power supply) when HSWAPEN is low which is suggesting to me that the FPGA is probably sleeeping. Maybe the suspend is not soldered on the PCB.

 

 

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Teacher eteam00
Teacher
6,804 Views
Registered: ‎07-21-2009

Re: Yet Another Spartan 6 Done pin low

I agree it should work, HSWAPEN when 0  enable a pullup on the suspend pin. butthe suspend pin is tied  to gnd with a 0 ohm resister therefore it should work.

 

Agreed that the suspend pin tied to GND is a requirement for a working design.

 

I cal also see less current (drained from the power supply) when HSWAPEN is low which is suggesting to me that the FPGA is probably sleeeping.

 

HSWAPEN has no effect on 'sleeping' state of FPGA.  NONE!  Its only purpose is to enable or disable weak pullup Rs on almost all IO pins in the period between powerup and completion of configuration.  This is thoroughly described in document UG381.

 

Maybe the suspend is not soldered on the PCB.

 

A poor connection on the suspend pin must be corrected for a working board.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Instructor
Instructor
5,049 Views
Registered: ‎08-14-2007

Re: Yet Another Spartan 6 Done pin low


@podericofrancesco wrote:

When HSWAPEN is LOW the FPGA doesn't seems to respond to Impact!

 

I don't think this is right! I believe it should still work am I missing something?

 

 


I can think of two reasons why HSWAPEN would interfere with configuration:

 

1) The HSWAPEN pin is shorted to another config pin or signal.  Removing the ground connection and monitoring the HSWAPEN pin for activity during configuration could confirm this.  It might be worth trying on another board, too.

 

2) Some pin or pins of the FPGA, when pulled high, cause some other on-board circuitry to become active and interfere with configuration.

-- Gabor
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5,037 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

Hi guys,

thank you for your help.

 

I think the FPGA has not soldered properly.

from the schematic the suspend pin isconnected to GND with a resistor.

I have removed the resister and connected the side connected to suspend to VCCAUX, while HSWAPEN was high, and the FPGA is not "sleeping". I can even access with IMPACT!

 

That proves that the SUSPEND pin is not soldered correctly to the FPGA, and I suspect other pins may be not connected as well.

 

I'll ask my customer to reflow the board and let you know if this has fixed the problem.

 

Thanks,

Francesco 

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Instructor
Instructor
5,031 Views
Registered: ‎08-14-2007

Re: Yet Another Spartan 6 Done pin low

Here's a quick check for connectivity you can do with a digital multimeter:

 

After removing the resistor to ground, put the multimeter in "diode check" mode.  Place the positive multimeter probe on ground.  Place the negative probe on the resistor pad that should connect to the FPGA.  If it is connected, you should see a diode voltage of about 0.5V, but if it is not connected the meter will show overload (or the max voltage drive depending on the meter).

-- Gabor
5,002 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

Hi Gabor,

 

good idea I have tried and I read 0.38V (approx) on both pads HSWAPEN + SUSPEND...so the FPGA is soldered correctly.

 

Now I'm confused.... why when I sold a wire between 3.3V and SUSPEND.... I can still use Impact!?

and why if I connect SUSPEND to GND and HSWAPEN to GND as well Impact doesn't work?

 

I'm very puzzled....

 

This morning I've been to a company to reflow the BGA as well...  getting confused...

 

any other idea? :-)

 

 

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Instructor
Instructor
4,997 Views
Registered: ‎08-14-2007

Re: Yet Another Spartan 6 Done pin low

It's still possible that there's a short circuit somewhere, and enabling the FPGA by grounding SUSPEND causes the FPGA to drive into the shorted net.

-- Gabor
4,692 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

Dear all I have completed the FPGA design and I'm now back to this problem. which I need to close in order to go in production.

I'm pretty sure the HW is OK now and I have found something possibly wrong, I need some experts like you two to help me on this please.

 

The Spartan-6 configuration file on page 82 states that in the bitstream after the syncronozation  I should have the Device ID  which should be :0xX400E093 (for a 6SLX75).

 

My hex file start with:

ffffffffffffffffffffffffffffffff

aa995566         // sync word

30a10007         // for a S6 LX75 I think this is wrong? it should be 0xX400E093 am I right?

 

 

if some guru at Xilinx could have a look please.

 

 

 

 

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Instructor
Instructor
4,685 Views
Registered: ‎08-14-2007

Re: Yet Another Spartan 6 Done pin low

Since this thread is getting old, and no Xilinx people have pitched in so far, I'd suggest starting a new thread with this question.  Otherwise it's likely that only those who previously subscribed to the thread will see it.

-- Gabor
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4,683 Views
Registered: ‎05-01-2014

Re: Yet Another Spartan 6 Done pin low

OK

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