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Explorer
Explorer
195 Views
Registered: ‎05-14-2017

startup primitive default setting connection

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The Ultrascale Kintex PCIe core has a block of signal from the STARTUP Primitive that are input which I need to tie high or low. They show up from the pcie3_ultrascale_0.vho

These signals appear on the pcie_ultrascale component when the Tandem feature is selected from the wizard.

PG156 doesn't describe how to connect them in my instantiation instance. The list of input signal are shown below. What document describe the condition or state required to connect them properly if I don't need them.

--    startup_do => startup_do,
--    startup_dts => startup_dts,
--    startup_fcsbo => startup_fcsbo,
--    startup_fcsbts => startup_fcsbts,
--    startup_gsr => startup_gsr,
--    startup_gts => startup_gts,
--    startup_keyclearb => startup_keyclearb,
--    startup_pack => startup_pack,
--    startup_usrcclko => startup_usrcclko,
--    startup_usrcclkts => startup_usrcclkts,
--    startup_usrdoneo => startup_usrdoneo,
--    startup_usrdonets => startup_usrdonets,

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Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎08-25-2010

回复: startup primitive default setting connection

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Hi @tchin123

 

Please refer to table 7-11,Pin Descriptions in ug570:

http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

 

Thanks
Simon
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Xilinx Employee
Xilinx Employee
168 Views
Registered: ‎08-25-2010

回复: startup primitive default setting connection

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Hi @tchin123

 

Please refer to table 7-11,Pin Descriptions in ug570:

http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

 

Thanks
Simon
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