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Observer murtaza5152
Observer
6,707 Views
Registered: ‎10-10-2011

AddSub block not working.

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Hello there!

 

I am facing a very weird problem with the AddSub block in one of my designs. Though the inputs are perfrectly fine, the output of my AddSub block is always undefined ("UUUU..."). I am using the block in the "user defined" unsigned output mode. it is very difficult for me to judge why the block is behaving in this manner as it works fine if i try it out in anotehr design. The AddSub blcok and rest of the design is generated by a Simulink model that I have attached. i am also attaching the output waveforms for your perusal.

 

Cheers!

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1 Solution

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Xilinx Employee
Xilinx Employee
5,345 Views
Registered: ‎02-11-2010

Re: AddSub block not working.

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When you include your project in ISE, it is necessary to workaround the issue by manually creating the "VHDL Libraries" you require and dragging in the necessary files from the work library. This is a known bug and a CR has been filed against this issue.

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24 Replies
Observer murtaza5152
Observer
6,706 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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The output waveform file is as attached. The output of the Addsub block is addsub_s_net and its inputs are mult_p_net and warp_num_in_net respectively.

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Xilinx Employee
Xilinx Employee
6,699 Views
Registered: ‎11-28-2007

Re: AddSub block not working.

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Your .mdl file simulates file in Simulink/SysGen. Are you instantiating this model in a Verilog/VHDL file and seeing the problem when running simulation in ISIM? If yes, I would double check that the VHDL files generated for the SysGen model are properly compiled with your ISIM simulation.

Cheers,
Jim
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Observer murtaza5152
Observer
6,696 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Yes. I am facing problems after I instantiated VHDL file of this model in a larger design. I check the VHDL files if the modules are connected properly if that is what you mean by checking for correct compilation for ISIM.
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Observer murtaza5152
Observer
6,688 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Guys,

I tried simulating the genrated block seperately and it works fine. Its only when I ma instantiating in a larger design the addsub block gives UNDEFINED output right from the start. I believe there is nothing to do with the correctb synthesis of VHDL file as it works perfect seperately. Also I see that all the enable signals, inputs etc. reach the Addsub block just fine.

 

I am clueless what might be happening!!?? :robotsad:

 

Please do let me know if you need any other information regarding this issue. I would appreciate your help.

 

 

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Observer murtaza5152
Observer
6,683 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Xilinx employees,

 

Need your help guys!

 

Can you tell me in what scenario the addsub block might give UNDEFINED outputs right from the start? There should be some particular condition that makes the output all "UUUUU" !!!

 

Cheers!

 

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Xilinx Employee
Xilinx Employee
6,680 Views
Registered: ‎08-02-2011

Re: AddSub block not working.

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Are you using a sysgen generated testbench or are you using your own?

 

Is it possible to post a project showing the issue?

 

You could also try generating a .ngc from sysgen rather than hdl and see if there is any difference

www.xilinx.com
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Xilinx Employee
Xilinx Employee
6,678 Views
Registered: ‎08-02-2011

Re: AddSub block not working.

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I just generated an .ngc with testbench from sysgen with  your .mdl and it simulates fine. No Uninitialized outputs. I suspect that it is an issue with how you're hooking it up to your larger design.

www.xilinx.com
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Observer murtaza5152
Observer
6,676 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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I am using  my own testbench. I am using the .ngc fule generated by sysgen for simulation. Even with my custom testbench, the design alone simulated just fine without any uninitialized outputs. 

 

Another experiment i did yesterday was to replace the addsub block with a mult block and the entire system simulates just fine. So there is some problem with the AddSub block!

 

 

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Xilinx Employee
Xilinx Employee
6,673 Views
Registered: ‎08-02-2011

Re: AddSub block not working.

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The addsub block seems to work everywhere except your custom design. Is it possible to post your project so we can see instantiation and what is driving your signals?

www.xilinx.com
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Observer murtaza5152
Observer
6,459 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Yes. I can do that. The entire system is not designed using simulink. There are a couple of blocks designed using simulink which are instantiated in a larger design. I am posting the top level design and other supporting modules.
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Observer murtaza5152
Observer
6,455 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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tb_warp_scheduler is the testbench to be used.

 

We are just concerned the outputs of two blocks under warp generator i.e. uWarpPerBlock and uWarpIdCalc.

 

The uWarpPerBlock gives the outputs just fine. The uWarpIdCalc is the one that used the simulink model containing the addsub block. If you see the output warp_id_out it is "UUUUU" right form the beginnning and this output is directly thrown out by that AddSub block.

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Observer murtaza5152
Observer
6,453 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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These are all the other files you will need. With these the entire project should be set up right and good to go.

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Xilinx Employee
Xilinx Employee
6,443 Views
Registered: ‎08-02-2011

Re: AddSub block not working.

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Looks like it's working to me (see attached). All the way out of the block, the outputs look good.

 

However, I have a few notes: Try using SysGen constant blocks instead of simulink->gateway in. It might make things a bit easier.

 

Also, your enable signal is being held low forever. Think about your clocking.

www.xilinx.com
Observer murtaza5152
Observer
6,438 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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I am wondering why all the inputs/outputs are zero iusing the testbench I gave you. But atleast your addsub output is not undefined. Attached is what I see in screenshot 1.

 

Also my enable input is not always zero. It goes 1 every N clock cycles as shown in the scrrenshot 2.

 

I am inclined to believe now if there there is something to do with the way you make your project (order of adding files may be) or the version of ise/isim i am running??

 

 

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Observer murtaza5152
Observer
6,436 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Also I cant use the Xilinx constant blocks because if I do that the input signals are only modelled as a bunch of nets as they are constants and the synthesized file does not give me input ports that I need as the inputs to warp_od_cal block are coming from another block.

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Observer murtaza5152
Observer
6,429 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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I figured out what exactly the problem is. It is because the addsub block of my warp_id_calc block is linked to the entity definitiomn xladdsub in warp_per_block_calc!!But if you see carefully, when you call a addsub block , you also pass a core_name as a generic parameter. So the addsub block in the warp_id_calc file looks for that particular core_name with xladdsub in warp_calc_block and obviously doesnt find it because it is NOT generated by warp_calc_block!!


So now how do i make my addsub block in warp_id_calc look ofr its definition in the same file and NOT link it to teh warp_calc_block file????


This makes so much sense and explains why they simulated correctly individually, why if i changed the addsub cblock to mult it worked(no mult block in warp_calc_block) and why the warp_id_calc chokes when simulated with the other file!!!
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Observer murtaza5152
Observer
6,421 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Ok. So finally this is done. I am getting the outputs correctly. 

 

I think there is a bug in the way Simulink generates the VHDL files / Xilinx ISE links the instantiation and the entity core together. So this is what happens.

 

I have a ADDSUB BLOCK in two different models "warp_id_calc" and "warp_per_block_calc". When you run Sysgen seperately on these files, both will generate entity "xladdsub" which is the structural description of the adder in both the files. What differentiates the two descriotions is the core name which is instantiated within each xladdsub as components. These components are different depending on the inputs and outputs of the particular adder.

 

now what happens when I add the two VHDL files is this. Say i add warp_per_block_calc first to the project, the addsub block within will be correctly linked to the xladdsub which is difined in this file. But when i add the next file "warp_id_calc", the addsub block in this file is linked to the xladdsub definition present in the the earlier file ("warp_per_block_calc"). And when it tries to find the core(instantiated as component) within xladdsub, it obviously cant find it because its defined in warp_id_calc file and not in the other one! Thus it can never find the adder definition even though it is there  as it is linked incorrectly !

 

The solution is to change the xladdsub name in the warp_id_calc to ssomething else and force it to find the entity in the same file and not the other file.

 

Hope this saves someone all the effort i had to go through to figure it out ! !

 

I would be grateful if someone from Xilinx can let me know if there is a neater way to add files or something else to amke sure files are linked correctly. Else, this might be a bug.

Thanks bwiec for your help. I appreciate it. 

 

P.S: Posted is the correct output. :) 

waveform_output.jpg
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Xilinx Employee
Xilinx Employee
6,413 Views
Registered: ‎11-28-2007

Re: AddSub block not working.

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The snapshot from the SysGen UG below talks about how to use different libaries for different models. Please check the UG for more additional information. (By the way, download Xilinx Document Navigator to manage all Xilinx documents) :ScreenHunter_40.jpg

@murtaza5152 wrote:

Ok. So finally this is done. I am getting the outputs correctly. 

 

I think there is a bug in the way Simulink generates the VHDL files / Xilinx ISE links the instantiation and the entity core together. So this is what happens.

 

I have a ADDSUB BLOCK in two different models "warp_id_calc" and "warp_per_block_calc". When you run Sysgen seperately on these files, both will generate entity "xladdsub" which is the structural description of the adder in both the files. What differentiates the two descriotions is the core name which is instantiated within each xladdsub as components. These components are different depending on the inputs and outputs of the particular adder.

 

now what happens when I add the two VHDL files is this. Say i add warp_per_block_calc first to the project, the addsub block within will be correctly linked to the xladdsub which is difined in this file. But when i add the next file "warp_id_calc", the addsub block in this file is linked to the xladdsub definition present in the the earlier file ("warp_per_block_calc"). And when it tries to find the core(instantiated as component) within xladdsub, it obviously cant find it because its defined in warp_id_calc file and not in the other one! Thus it can never find the adder definition even though it is there  as it is linked incorrectly !

 

The solution is to change the xladdsub name in the warp_id_calc to ssomething else and force it to find the entity in the same file and not the other file.

 

Hope this saves someone all the effort i had to go through to figure it out ! !

 

I would be grateful if someone from Xilinx can let me know if there is a neater way to add files or something else to amke sure files are linked correctly. Else, this might be a bug.


 

Cheers,
Jim
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Observer murtaza5152
Observer
6,407 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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So when I do this switching it relaces all the references to the work library to corresponding library names. But the UG hasn't mentioned how do I add those libraries to my project. If I just run my project after running the xlswitch command and replacing the corresponding files, it complains about NOT being able to find the libraries by those name that i gave in the xlswitch command!

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Xilinx Employee
Xilinx Employee
5,346 Views
Registered: ‎02-11-2010

Re: AddSub block not working.

Jump to solution

When you include your project in ISE, it is necessary to workaround the issue by manually creating the "VHDL Libraries" you require and dragging in the necessary files from the work library. This is a known bug and a CR has been filed against this issue.

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Observer murtaza5152
Observer
4,444 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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OK. So I created different libraries and now the entities are properly linked. However in the ISIM simulation,these entities are not recognized at all. i.e I don't see them. 

 

How do I get around this? How do I compile the libraries I created in the project?

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Observer murtaza5152
Observer
4,434 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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Can anyone please help me with the above issue?

To reiterate, I added the two entities in two different libraries and the linking problem is gone. But it seems that ISIM doesn't recognize entities other than the ones in the work library.

This is attested because, I cant see those entity .vhd files in the "Source Files" tab of ISIM.

Any help is appreciated a lot !

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Observer murtaza5152
Observer
4,427 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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In short, ISIM is not recognizing the user defined libraries!! :-o
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Observer murtaza5152
Observer
4,425 Views
Registered: ‎10-10-2011

Re: AddSub block not working.

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I figured it out. I just had to mention the library names in the top level file that is using the entities in the user libraries.

So now I have the complete procedure to use multiple sysgen file in a project.

I hope this bug is sorted out ASAP to save people from all the trouble. It's indeed very difficult to recognize this issue at the first place ! Trust Me !
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