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Adder/Subtracter IP latency (PG120)

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Voyager
Posts: 380
Registered: ‎10-07-2011

Adder/Subtracter IP latency (PG120)

To Xilinx folks!

 

I'm trying to find out what the latency of the Adder/Subtracter IP core is going to be when automatically computed (that is optimal value).

 

So far, my findings are that it only depends on the bit width of both the A and B operand.

 

Latency = ceil(maximum(A,B) / 12);

 

Can you (Xilinx) confirm the above equation is right?

 

In general, it would be very helpful to provide that equation in the IP PGxxx. That would allow us to automatically compute the depth of our delay lines when using IPs into pipelines.

 

Thanks!

 

Claude

 

Scholar
Posts: 2,626
Registered: ‎07-09-2009

Re: Adder/Subtracter IP latency (PG120)

Im guessing some university Tutor is asking this question , as it keeps coming up,

 

In programmable logic, there is no such thing a latency,

 

The tools fit your design to meet your timing and stop.

 

An IP is just a bunch of code,

   it is not fixed as to where it goes in the chip,

      

Different parts / routes on a chip have different propagation time,

   The tools also have things like the fast carry chain or the built in DSP block

       which also affect propagation time

 

 

 

     

 

 

so you can not come up with an equation for an adders speed,

      

Voyager
Posts: 380
Registered: ‎10-07-2011

Re: Adder/Subtracter IP latency (PG120)

Thanks for your comment however, I feel like your missing the point.

 

I'm not asking for the worse propagation time and maximum achievable clock frequency, but for the number of clock cycles from the time data is presented at the input, to the time the corresponding result appears at the output. All of this because of the register stages that are embedded into the adder and are making it pipelined.

 

I ran some test with different configuration parameters and so far, it seems like it only depends on the bit width of the wider of the 2 input operands, A and B. It seems that the optimal latency is equal to ceil(max(A'length,B'length)/12). That's what I'd like Xilinx folks to confirm and what I think should be useful in the PGxxx.

Advisor
Posts: 543
Registered: ‎01-22-2015

Re: Adder/Subtracter IP latency (PG120)

[ Edited ]

 @chevalier

 

So many things to talk about with the Xilinx IP called Adder/Subtractor that is described by document, PG120.  Prepare yourself for my rambling….

 

  1. Old Fashion: This IP does simple addition and subtraction. I don’t recommend using it because…. New Fashion is better.

  2. New Fashion: Nowadays, the need for addition or subtraction is simply expressed using HDL (as shown by the following VHDL example) - and we let synthesis figure out the rest.
    signal S, A, B  : unsigned(N downto 0);
    …..
    p1 : process(clk1)
    begin
       if rising_edge(clk1) then
           S <= A + B;
       end if;
    end process p1;
    The new fashion approach makes your code portable and usually passes timing analysis (ie. the calculation has a latency of 1 cycle of clk1). That is, synthesis will often use fabric combinational logic to do the math.  When things get tough (eg. lots of bits in S,A,B) then synthesis will use the DSP48 without pipelining (which is also just combinational logic).  However, when the HDL fails timing analysis then you can usually make it pass timing analysis by adding a register (or two) as shown below to pipeline the DSP48.
    signal SP, S, A, B  : unsigned(N downto 0);
    …..
    p1 : process(clk1)
    begin
       if rising_edge(clk1) then
           SP <= A + B;
           S <= SP;
       end if;
    end process p1;
    With the pipeline register, SP, the calculation of S is finished in two cycles of clk1 after inputs A and B are asserted (ie. the calculation has a latency of 2 cycles of clk1).

  3. In IP Wizard, Where is Clock Frequency?: The wizard for the Adder/Subtractor IP makes no mention of clock frequency ! ! PG120 talks about an “Automatic” setting whereby you can “achieve optimal pipelining for maximum speed”. -but, what’s the speed?  Well, PG120 gives a partial answer by referring you to a website  <Performance and Resource Utilization web Page>. However, the website gives speed for only certain bit widths.  Uhmm… why can’t the IP tell us what the website says … and much more?  Yet another reason I don’t recommend using this IP.

 

                     Latency = ceil(maximum(A,B) / 12);   Can you (Xilinx) confirm the above equation is right?

A missing design equation!  Yet another reason I don’t recommend using this IP.

 

Cheers,

Mark

 

Scholar
Posts: 2,626
Registered: ‎07-09-2009

Re: Adder/Subtracter IP latency (PG120)

wonder is the  / 12 , dependent upon the chip

 

wonder what the limit is, If I put A as 128 and B as 54,   or A as 100000 and B as 100 , would the equation hold true,

    

wonder what happens in Ultra plus, with multiple die interconnect, if the adder has to go across die's ?

 

wonder how does the carry in being used or not affect the numbers ?

 

Would be interesting to know ,

 

Voyager
Posts: 380
Registered: ‎10-07-2011

Re: Adder/Subtracter IP latency (PG120)

Hello markg@prosensing.com and @drjohnsmith,

 

Thank you guys for your comments! Always appreciated to get hints.

 

Mark, I agree with you and would love to use plain HDL rather than the IP. However, refering to your comments:

  1. I think the IP basically adapt (optimize) the resources based on the target architecture. It is possible than longer carry chain can be achieved on Zynq UltraScale+ than on Artix-7.
  2. I'd like to use plain HDL but it means I would have to code the adder such that it can break large values (eg 64 bits) into multiple smaller values (eg 4x 16 bits or 8x 8 bits, whatever is better dealt with on the target device, with respect to the length of the carry chain), and cascade the sub-additions. This would for sure work efficiently and reliably but would have significantly higher latency than the Xilinx IP.
  3. I think IP clock frequency is derived from the selected target family. I thought the /12 factor from my equation would vary from a family to the other but it's the same for Zynq UltraScale+, Virtex UltraScale+ and basic Artix-7 (didn't try other families).

John, partial answers to your questions:

  1. See 1 and 3 above.
  2. The Xilinx IP is restricting the size of A and B from 2 to 256.
  3. The equation looks OK over that entire range, and for both Zynq UltraScale+, Virtex UltraScale+ and Artix-7.
  4. I don't think an IP can go across part boundary. Signals going across dies shall be IP interface signals rather than IP internal signals.
  5. Enabling the carry input doesn't seem to impact the latence. The latency equation still looks valid. In fact, none of the options available in the configuration wizard seem to impact latency other than the bit width of the A and B operands.

Xilinx, we still need to hear from you!

The IP wizard is somehow calculating the so-called "optimal latency". How is that value computed? Can you provide the maths for that and document latency in PG120?

 

Cheers,

 

Claude

 

Scholar
Posts: 2,626
Registered: ‎07-09-2009

Re: Adder/Subtracter IP latency (PG120)

@chevalier

 

good luck with your work,

   Im really not certain where your going, 

 

as others have said, the days of using the IP blocks for adder are long gone,

       The tools are very good at register push back and optimisation,

             

This level of IP is just not the way things are done,

     the tools do so much optimisation, that this level is just not productive,

  

As for splitting numbers up to fit them into the carry chain,

   again, see what the tools do after synthesis to native HDL.

 

FYI, the way I work is

   everything in HDL, its re usable across projects and devices

      if design does not meet timing, then look where problem is and address.

 

 

          

 

   

Voyager
Posts: 380
Registered: ‎10-07-2011

Re: Adder/Subtracter IP latency (PG120)

@drjohnsmith

 

Thanks! These are good advices. Regarding

    As for splitting numbers up to fit them into the carry chain,

        again, see what the tools do after synthesis to native HDL.

 

Is this documented somewhere??? Or is it a matter of coding it and see on it gets synthesized (ie trial and error)?

 

Cheers,

 

Claude

 

Scholar
Posts: 2,626
Registered: ‎07-09-2009

Re: Adder/Subtracter IP latency (PG120)

The ultimate reference would be the 

 

https://www.xilinx.com/products/design-tools/ultrafast.html

 

But its down to experience ,