UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer oscaro
Observer
1,921 Views
Registered: ‎06-05-2018

DDS compiler V6 question

We have a receiver chain where there will be a 400mhz BW signal that we are sampling with an ADC at 2GSPS. After the ADC we have a DDS followed by sinc filters do down-convert and inverse sinc fitlers to compensate.

 

The FPGA fabric is not going to run at 2GHZ rate, at most lets say we can do 400mhz.  One trick I have heard from some

of my colleagues is to have a set of 5 parallel DDS in which each DDS is  phase shifted by 2pi/5 from the other. So you create

5 streams of data which are down sampled by the FIR filters after the DDS.

 

  After the filters you combine the 5 streams in the order that they are shifter in (phase shift 1 sample is taken first then phase shift sample is taken next) to generate a final single data stream at a slower rate.

 

The first experiment I did was to create a DDS IP with the V6 DDS compiler using programmable mode and have it so the input clk is 400mhz the output frequency is 200mhz.

 

I simulated the demo test bench that gets generated with the IP and they had two values coming into the phase increment and offset:

 

    s_axis_config_tdata(29 downto 0) <= "100000000000000000000000000000";  -- phase increment

    s_axis_config_tdata(61 downto 32) <= "000000000000000000000000000000";  -- phase offset

 

    s_axis_config_tdata(29 downto 0) <= "010000000000000000000000000000";  -- current phase increment / 2

    s_axis_config_tdata(61 downto 32) <= "100000000000000000000000000000";  -- current phase offset + PI radians

 

The first set of values gave me a fixed cosine of 1 and sine of 0 (cosine had a small ripple), which based on the DDS GUI it should have given me ½ of the input frequency (200mhz).

 

Once we moved to a different set of input values it gave us a square wave of ½ the frequency of the input clk as we wanted). However, the GUI says that for a frequency of 200mhz (or ½ the input clk) a phase increment of

"100000000000000000000000000000" should have given us 200mhz.

 

The simulation model is wrong or the GUI is incorrect, or I am missing something???

 

I then modified the demo test bench and tried instantiating 5 DDS blocks (400mhz *5 = 2ghz). And gave each an offset of 2pi/5 (I put in 0, 0.2, 0.4. 0.6, 0.8), it did not give me a phase offset that I expected and the frequency went down even further (1/4). The output with the offset of zero was as before (1/2 the frequency but only after changing the value to X’1000000 instead of X’2000000 as the gui says.

 

Is the fact that the output to input frequency ratio is only 1:2 the problem? In other words to have enough resolution to get us 1/5 or perhaps 1/8 phase offset resolution then the output to input ratio has to be much

greater?

 

If this is the case, how much of a ratio do we need get the phase resolution we need of let say 1/5 or 1/8?

 

Another requirement that is imperative is that when we program a new phase increment and offset the delay between the strobe of config_tvalid to new frequency and phase starting

be the same each time (deterministic). This is required to keep coherence… for example if we start it out at time zero with a frequency x and offset y then when we change to a new frequency and offset the new waveform

coming out of the DDS has to be as if it had started at the same time zero also….naturally we would program it with the correct phase offset that it needed to have to be coherent only

if we know how long it will take to start out and compensate for that delay in our offset value. So again, is the delay the same each time one changes frequency and offset??

 

 

The_top_level.jpg
0 Kudos
25 Replies
1,912 Views
Registered: ‎06-21-2017

Re: DDS compiler V6 question

A 200 MHz sine wave sampled at 400 MHz will alternate between two values.  The DDS is doing exactly what it is programmed to do.

0 Kudos
Scholar drjohnsmith
Scholar
1,910 Views
Registered: ‎07-09-2009

Re: DDS compiler V6 question

For my own interest,

 

Assuming you really have a 400 MHz bandwidth in ? ( not milli Hz ) sampled at 2G

Nyquist, you need at least 800 M sample rate to represent this,

    so you can max decimate by just over two , 2000 / ( 400 * 2 ) 

 

 

 

0 Kudos
Contributor
Contributor
1,817 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question


@oscaro wrote:

 

I simulated the demo test bench that gets generated with the IP and they had two values coming into the phase increment and offset:

 

    s_axis_config_tdata(29 downto 0) <= "100000000000000000000000000000";  -- phase increment

    s_axis_config_tdata(61 downto 32) <= "000000000000000000000000000000";  -- phase offset

 

    s_axis_config_tdata(29 downto 0) <= "010000000000000000000000000000";  -- current phase increment / 2

    s_axis_config_tdata(61 downto 32) <= "100000000000000000000000000000";  -- current phase offset + PI radians

 

The first set of values gave me a fixed cosine of 1 and sine of 0 (cosine had a small ripple), which based on the DDS GUI it should have given me ½ of the input frequency (200mhz).

 

Once we moved to a different set of input values it gave us a square wave of ½ the frequency of the input clk as we wanted). However, the GUI says that for a frequency of 200mhz (or ½ the input clk) a phase increment of

"100000000000000000000000000000" should have given us 200mhz.

 

The simulation model is wrong or the GUI is incorrect, or I am missing something???  


 

I believe there is an issue with the auto generated test bench and how configuration parameters are applied to the DDS IP during simulation.  When I use the auto generated test bench I see the same thing as you.  The cosine output is stuck at 1 and sine at 0.  When I modify the test bench to apply the config parameters to the DDS IP from a clocked process in the test bench then I see the cosine values toggle between +/-1 and the sine is 0, which is the expected behavior for a 200 MHz output.  


@oscaro wrote:

 

I then modified the demo test bench and tried instantiating 5 DDS blocks (400mhz *5 = 2ghz). And gave each an offset of 2pi/5 (I put in 0, 0.2, 0.4. 0.6, 0.8), it did not give me a phase offset that I expected and the frequency went down even further (1/4). The output with the offset of zero was as before (1/2 the frequency but only after changing the value to X’1000000 instead of X’2000000 as the gui says.

 

Is the fact that the output to input frequency ratio is only 1:2 the problem? In other words to have enough resolution to get us 1/5 or perhaps 1/8 phase offset resolution then the output to input ratio has to be much

greater?

 

If this is the case, how much of a ratio do we need get the phase resolution we need of let say 1/5 or 1/8?  


 

Testing with a phase offset of 2pi/5 ("001100110011001100110011001100" - 30-bit phase) shows the cosine value alternating between +/- 0.30896 and the sine value alternating between +/- 0.95101 every clock cycle. 

 

Testing with a phase offset of 4pi/5 ("011001100110011001100110011001" - 30-bit phase) shows the cosine value alternating between -/+ 0.80896 and the sine value alternating between +/- 0.58774 every clock cycle. 

 

What output values are you seeing?  Maybe the configuration issue with the auto generated test bench noted above is causing you issues here as well.

 


@oscaro wrote:

 

Another requirement that is imperative is that when we program a new phase increment and offset the delay between the strobe of config_tvalid to new frequency and phase starting be the same each time (deterministic). This is required to keep coherence… for example if we start it out at time zero with a frequency x and offset y then when we change to a new frequency and offset the new waveform coming out of the DDS has to be as if it had started at the same time zero also….naturally we would program it with the correct phase offset that it needed to have to be coherent only if we know how long it will take to start out and compensate for that delay in our offset value. So again, is the delay the same each time one changes frequency and offset??  


 

Yes, it should be.  In the Detailed Implementation of the DDS IP customization menu you have a couple of latency options.  The auto option allows Vivado to configure the latency which is reported in the drop-down menu. 

 

dds_ip_lat1.png

 

You can also change the latency to a different value using the Configurable setting.

 

dds_ip_lat2.png

0 Kudos
Observer oscaro
Observer
1,713 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

So I got this to simulate. I have 5 DDS instantiated each one has a phase shift of 1/5pi, so I have programmed the following

phase shifts in: 0, 1/5pi, 2/5pi, 3/5pi, 4/5pi. (0, 0.2pi, 0.4pi, 0.6pi and 0.8pi).

 

They put out the correct frequency and magnitude except for the one for 0 phase offset. That one the output is railed at -26d33444431 for cosine and 26d0 for sine.

 

 I need to have 5 different phase shifts so how can I make the 0 phase offset work.

 

I tried shifting the first one a bit by doing 0.1, 0.3, 0.5, 0.7, 0.9 but I still have the same problem with the one for 0.1.

 

Any way to get this to give me an output on 0 phase shift?

Results_tb_0_dds_400mhz_in_200mhz_out_IP_at_200mhz.jpg
0 Kudos
Contributor
Contributor
1,707 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

For phase offset of zero, I'd expect the sine output to be stuck at 26d'0 since sin(0 + N*pi) = 0 for all N, where N is the output index.  However, the cosine value should toggle between +/- 26d'33444431 (+/- 1).  When I run a simulation with 0 phase offset I see the cosine output toggle between +/- 1 (image below).  There could be an issue with your simulation environment and/or test bench. Have you tried running in the Vivado simulator instead of ModelSim?

 

dds_ip_outputs_phase0.png

 

When I simulate with 0.1*pi offset I see the cosine output toggle between +/- 0.9510 and the sine output toggle between +/- 0.3090.  So, that is working for me as well (see screenshot below).  This seems like a simulation environment issue.   Any chance you can attach your IP configuration and test bench?

 

dds_ip_outputs_phase0.1pi.png

 

I've attached the test bench I'm using with Vivado simulator.  I've modified it to stimulate the configuration port from a clocked process instead of the asynchronous process that is auto-generated when the IP is created. 

0 Kudos
Observer oscaro
Observer
1,695 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

So as per your suggestion I switched to the Vivado simulator and got the same problem I am having with ModelSim when I run the

simulation inside of the Vivado Gui (I could not fix this so I started running Modelsim from outside the GUI).

 

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation
[USF-XSim-62] 'elaborate' step failed with error(s) while executing 'C:/Users/oo/Documents/myrepos/gforge/Transceiver/Vivado 2018.1/TX_DDS.sim/sim_1/behav/xsim/elaborate.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
[Common 17-180] Spawn failed: Broken pipe

 

This broken pipe stuff has cost me quite a bit of time and I am quite frustrated at this tool... I am running version 18.1 of Vivado so it is pretty up to date...  Gee Altera's Quartus sure works all the time.

 

 

0 Kudos
Scholar drjohnsmith
Scholar
1,682 Views
Registered: ‎07-09-2009

Re: DDS compiler V6 question

I can assure you that the tool you mention do not work all the time as you state

 

I have quiet a few valid bits of code that have been submitted over the decades, and still wont work in the other tools but do in Xilinx tools.

 

yes I hate Vivado, 

 

I hate the way its moving to script only

 

I hate the way Xilinx is abandoning Vhdl 

 

but not this part of vivado

 

 

 

Can I take step back,

 

do you think its the tools or the IP thats is at fault ?

 

 

0 Kudos
Contributor
Contributor
1,661 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

 

When the new phase & offset are applied to the configuration port, is config_tvalid only high for 1 clock cycle?  Maybe try holding it high for multiple clock cycles, or just tie it to '1' and see if that does anything.  Just trying to see if there is an issue causing the configuration to not be accepted by the IP core.

0 Kudos
Highlighted
Observer khal
Observer
1,602 Views
Registered: ‎03-03-2017

Re: DDS compiler V6 question

oscaro, you might want to check out following free DDS IP core written in HLS: Zotech DDS IP core

0 Kudos
Observer oscaro
Observer
1,617 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

Hi Dsp81,

 

 I simulated your testbench and it worked like you said. So I went back to my testbench and noticed that while doing a copy of values I messed up and had the wrong values going into the DDS that was supposed to get the 0 offset. Once I fixed that it worked.

 

Now, I noticed you put 3333333 for 0.1 phase offset (maybe I have understood this wrong as I have 6666666 for 0.1. In the gui I entered that I wanted as an offset of 0.1 and it gave me a value of 666666). How did you come up with 3333333? It looks like you put 0.05... that is the only way I got 3333333 as a value.

0 Kudos
Contributor
Contributor
1,609 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

oscaro,

 

You are correct, 0x03333333 is equal to 0.05 cycles.  When we multiply by 2*pi for a full cycle we get 0.1*pi.  Make sense?  

0 Kudos
Observer oscaro
Observer
1,595 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

Hi Dsp81

 

So the way I was thinking about it was 0.1 phase offset with respect to the full cycle....I am not sure why we have to end up with 0.1pi (pi being 180deg). Shouldn't we think in terms of the full cycle?

0 Kudos
Contributor
Contributor
1,585 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

 

You can definitely think of it in terms of cycles instead of radians.  So, you could use offsets of 0.1, 0.3, 0.5, 0.7, 0.9 cycles. 

 

In my previous post I was just commenting that if you want a phase offset of 0.1*pi radians, which is what is shown in the simulation waveform, then you would need to set the offset in cycles to 0.05 (config value of 0x03333333). 

 

 

0 Kudos
Observer oscaro
Observer
1,506 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

My current IP that I generate has 30 bit input for both the phase increment and phase offset values. The outputs are signed 26 bits.

 

Is there a way to calculate the delta that the DDS should do for a 1 LSB change in both or those?

 

Mode of operation is standard,

400mhz input clk,

number of channels: 1,

amplitude mode: full range,

Spurious free dynamic range: 150,

Frequency resolusiton 0.51 hz,

noise shaping: auto (Taylor Series Corrected)

 

Thanks!
Oscar

0 Kudos
Scholar drjohnsmith
Scholar
1,498 Views
Registered: ‎07-09-2009

Re: DDS compiler V6 question

my maths is a little rusty , so I'll leave that part to some one else,

 

but , you say SFDR of 150 , is that db ?

 

that seems very large ,,,  thats 25 bits or so of SFDR ..

   you have a DAC / NCO with that range ?

 

 

0 Kudos
Observer oscaro
Observer
1,461 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

You are right...my adc is going to be at most 14 bits wide so that should be 84db. I have to go back and change that. I think when I first started looking at the DDS I just put the max value and never went back to change it.

0 Kudos
Contributor
Contributor
1,453 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question


@oscaro wrote:

Is there a way to calculate the delta that the DDS should do for a 1 LSB change in both or those?


oscaro, just want to make sure I understand your question correctly.  Are you asking what the output of the DDS would be for a 1 LSB change of the phase increment and/or phase offset inputs?  Or, are you asking what values of phase increment/offset are necessary to change the output by 1-bit?  

 

 

 

 

0 Kudos
Scholar drjohnsmith
Scholar
1,448 Views
Registered: ‎07-09-2009

Re: DDS compiler V6 question

it 'normal' to make the input to the phase  to sine block 3 or 4 bits greater than the dac used,

    any more is a waste,

 

 

0 Kudos
Observer oscaro
Observer
1,439 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

I was wondering how do I calculate the change in frequency for a change of one LSB jn phase increment.

0 Kudos
Contributor
Contributor
1,331 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

PG141 gives the following for output frequency in standard mode:

 

dds_output_freq.png

 

Dq is the phase increment.  I'd recommend reading through chapter 3 of PG141, if you have't already because there is a lot of good information.  

0 Kudos
Observer oscaro
Observer
1,323 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

So I did an experiment where I changed the phase increment from:

20000000  to 20000005 to get a 2hz delta in frequency (gui say the actual value is 200.0000186...). I did not see that in the

simulation. This is probably a simulation model accuracy? problem or in the real

IP it may average to that 2hz difference.

 

Thoughts?

 

 

0 Kudos
Scholar drjohnsmith
Scholar
1,303 Views
Registered: ‎07-09-2009

Re: DDS compiler V6 question

A raw DDS can only make certain frequencies,

 

so if your design can not make 2 Hz step, the gui will show that,

 

If you want 'any frequency' then your into the world n /n+1 frequency synthesis , and a real alog pll on the output.

 

As for simulation, 

 

 

do you think you would see 2 Hz delta in 200 MHz ? 

 

200 MHz is 5 ns,   200.000002 MHz is 4.99999995 ns...

 

how many hours did you simulate over ?

  whats your simulator resolution,

 

 

0 Kudos
Contributor
Contributor
1,287 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

Keep in mind that anything over 200 MHz will violate the Nyquist sampling theorem when sampling at 400 MHz.  

 

Edit: just noticed you said 2 Hz instead of 2 MHz.  It looks like the closest you can get to a 2 Hz step with 30 phase bits is 1.86 Hz.

0 Kudos
Observer oscaro
Observer
1,249 Views
Registered: ‎06-05-2018

Re: DDS compiler V6 question

 

   You said anything above 200mhz will violate Nyquist, but the interesting thing is that the GUI says valid range of output

frequency is 0.0 to 400mhz. So can we actually go above 200mhz or not?

0 Kudos
Contributor
Contributor
1,243 Views
Registered: ‎10-25-2017

Re: DDS compiler V6 question

The IP will let you select a frequency above 200 MHz, but I believe it will be aliased.  For example, if you select a 250 MHz output and sample that at 400 MHz you will get something that looks like a -150 MHz sine wave. 

0 Kudos