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Newbie emad.rajabi
Newbie
2,455 Views
Registered: ‎09-08-2010

Detect sign of a signal

I'm currently working On QPSK system.Now after demodulation I have problem detecting the value of I and Q signal...

For this purpose I have written a vhdl file but it does not detect the sign correctly and also the timing is not correct..

I don't know what's wrong and what can I do?

 

Also there is a verilog file which one of my friend Lemoon wrote that,it works perfectly.But I don't have any verilog information.And also because of using some delay in that verilog I'm not sure if it could be synthesized.!(I'm not sure)

 

the signal that I want to detect its sign ,is something like this:

 

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Xilinx Employee
Xilinx Employee
2,384 Views
Registered: ‎11-28-2007

Re: Detect sign of a signal

When you do math (addition, subtraction, comparison, etc) in VHDL, you need to be always aware what type of operands (signed vs unsigned) you are dealing with and then go from there. Hopefully the document below can clear something up:

 

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

 

 

Cheers,
Jim
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