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Observer s_aelsok
Observer
4,232 Views
Registered: ‎03-19-2012

Exporting shared FIFO - Free running clock mode

Hi all,

 

I am using a blackbox with a VHDL description of a circuit that uses two different clocks, one is generated from sysclk and the other from an external reference input to an mmcm.

It should be run in Free-running clock mode, I imported it in a blackbox in system generator. However to interface with it, I have put a shared FIFO (to FIFO block - its name is 'Bar' ) but I need the writing clock to this FIFO as a clock that is from the blackbox (not from sysclk) .

 

Is it possible to export the netlist of the (to FIFO) , and then add it as a component in the vhd file of the blackbox now the black box would contain my vhdl file and (to FIFO) ? ,

How to read from it ?  

Would the shared memory configured as FIFO still see the name 'Bar' ?, as I didnt find any specification of  the name 'Bar' in the netlist or any of the generated files for the exported (to FIFO) block.

 

Thanks in advance, 

 

regards,

Ahmed.

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2 Replies
Xilinx Employee
Xilinx Employee
4,220 Views
Registered: ‎08-01-2007

Re: Exporting shared FIFO - Free running clock mode

Running HW-CoSim with a shared memory can be a bit tricky.  You will probably want to run in free running mode, but make sure you are following the provided examples that show how to use the shared memories with HW-CoSim.  They can be found in the System Generator for DSP User Guide.

Chris
Video Design Hub | Embedded SW Support

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Observer s_aelsok
Observer
4,217 Views
Registered: ‎03-19-2012

Re: Exporting shared FIFO - Free running clock mode

Hi Chris,

thanks for your suggestion and reply, 

ok, let me tell the full story, which is a little long , pretty informative though,  so please bear with me.

 

I know how to run shared memories with a free running clock pretty well in system generator, I  have been simulating my DSP algorithm (which I made in system generator) in this way .

 

kit : virtex6dsp = ML605 , FMC150 AD/DA .

 

Now I would like to apply it to real time signal sampled by the FMC150 A/D .  I have made the interface to it in a vhdl file , including SPI, LVDS, iDDR ... and an mmcm (multi-mode clock manager) to get the clock from the ADC. I have defined nmm ports (adc SPI_data , SPI_clock, cha_lvds (from ADC), clock_from_adc .... and all ports necessary for ADC operation) and made a custom ML605 board for JTAG cosimulation.

 

sample rate : 61.44 MSPS.

sysclk : J9,H9.

 

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Bad appraoch:

Now the shared memory takes the output from the ADC using the sysclk (J9,H9). which results in oversampling. I would like to avoid this. So what I was trying to do , was to make a block with the shared (to FIFO), get its ngd,vhd , import it in the blackbox from my ADC vhdl code , make its clock the sampling clock from ADC.

 

However ... its other half (shared memory) is outside the black box, in the file that has the cosim block, now how would system generator know the name of the memory that I have inside ... so that's why I dont think this will work.

-----------------------------------------------------------------------------------------------------------------------------------------------------

 

What I'm doing now


So currently, I have made a native assymetric-clock FIFO for xilinx Core generator, added it in my interface, where the write clock is the sampling clock, and the read clock is the sysclk from the system generator.

 

so now I have 2 FIFO's, 1 in vhdl (native - coregen) and 1 in system generator (shared FIFO to see an output that makes sense with free running clock) and this works to have some outputs of the ADC (as much as the native FIFO depth) and display them in simulink ... and this works fine.

 

My problem:

Currently I'm having a different issue ... I would like to add my algorithm after the ADC ... when I add it directly after the blackbox containing the ADC interface, sysgen complains about rate propagation of the enable signal to my algorithm ( I have an enable from the ADC when the data is valid - i.e. the mmcm is locked)

 

So I don't know how to overcome this ( how to convince the system generator to read this enable signal at the sysclk rate).

 

Another question ...  is it possible to make the clock of my algorithm (or the sysgen sysclk sort of say) the clock output of the mmcm that I put to the clock from ADC, because this clocking thing is driving me crazy :) ? 

the ADC (infact the FMC150 clocking tree) outputs an LVDS DDR clock, that needs an IDELAY to be applied ( which I already do in my interface) to align with the data-in from ADC.

 

Is it possible to tell system generator to take this clock as the sysclk ? 

I tried to play with multiple system generator, however still I cannot tell it to take the sysclk form the ADC clock pins.

 

Thank you very much for spending time reading this... 

Please tell me if you have any suggestions or comments. 

 

Best Regards,

Ahmed

 

 

 

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