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Observer thunderdan
Registered: ‎08-29-2011

Exuberant compile time for HDL Netlist



ISE 13.2

Virtex6 (ML605 dev kit)


I'm have no idea how long a system generator project to compile to a HDL netlist is supposed to take, but so far I've been waiting well over an hour. Is this normal? Xilinx blockset design isn't huge, ( Simple AM demodulator so a few filters, squarer etc) I don't have this problem when running HW co simulation, only now when I'm trying to add a system generator (sgp) source to ISE. I thought it just produced VHDL code?


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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

Re: Exuberant compile time for HDL Netlist

Compilation time can vary.  Usually it has to do with how large and full your part is, and how difficult your timing constraints are to meet.  If you are trying to run at a high frequency that can cause the compilation to be longer because it might not be easy for the tools to meet the requested timing.

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