UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
393 Views
Registered: ‎03-27-2014

Faulty DDS behavior

Hello,

 

I tried to overclock the DDS IP core by adding the clock enable bit, but TVALID from the output data bus does not reflect this bit activity (at least in simulated behavior, but because of that I have not pushed it further).

 

I know the idea behind the DDS is to produce one sample per clock cycle, but in this situation TVALID should only be asserted when clk enable is '1', otherwise you will end up oversampling the output data. 

 

 

G.W.,
NIST - Time Frequency metrology
0 Kudos
1 Reply
Moderator
Moderator
353 Views
Registered: ‎08-01-2007

Re: Faulty DDS behavior

The DDS does not provide the oversampling feature.

0 Kudos