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Participant
7,378 Views
Registered: ‎10-31-2011

## Floating Point processing strategy

Hello,

I feel I'm getting perplexed trying do develop mathematical operation, that involves many float-point multiplications (also adding/substractions).

The mathematical function is:

c0 = a00*a11*a22 + 2.0*a01*a02*a12 - a00*a12*a12 - a11*a02*a02 - a22*a01*a01;

where a00 ... a22 - real numbers.

a00 = 4.578873857871106e+003

a01 = -1.110544415573152e+002

a02 = 1.510942250588750e+003

a11 = 1.521703241783251e+003

a12 = -9.562066504027414e+002

a22 = 1.055255716792533e+003

The problem is to construct Simulink/Sysgen model that deliver a result as close as possible to Matlab realisation.

In my model (please see the picture) more or less satisfying result is obtained when I set Gateway In precision as follows:

Output Type : unsigned

Number of bits : 48

Binary point : 30

The precision settings for the blocks that involved in processing (all the Multipliers and Adders/Substractors) I set to Full.

Is there some approach that would get a suggestion concerning precision settings for Multpliers and Addders/Substractors (instead of Full precision) after simulation of several datasets.

Pavel.

1 Solution

Accepted Solutions
Xilinx Employee
7,055 Views
Registered: ‎08-02-2011

## Re: Floating Point processing strategy

True that the FPO core was supported. But the SysGen FP blocks didn't exist previously. Look in your library browser... is there a Floating Point blockset in SysGen, similar to my 13.3 install shown here

www.xilinx.com
17 Replies
7,375 Views
Registered: ‎08-20-2007

## Re: Floating Point processing strategy

The problem is that FPGA natively works with fixed point.

I think it worse first to define the dynamic range of your inputs - E.g what is the minimum and maximum number can be represented in a00...a22. In your other post you said, that they are coming from another FPGA block. What is the output signal dimensions of that block?

And then I think you need to define a tolerance of result. This will be an absolute value I think.

Participant
7,373 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

Hello Syoma,

Thanks for response.

@syoma wrote:

The problem is that FPGA natively works with fixed point.

I think it worse first to define the dynamic range of your inputs - E.g what is the minimum and maximum number can be represented in a00...a22. In your other post you said, that they are coming from another FPGA block.

For the moment I can't define min/max limits, but it will be done. For this task to be accomplished I need to process (or medelize) different datasets. Previous FPGA block isn't designed yet - its algorithm is implemented into a Matlab function, that does processing job.

@syoma wrote:

And then I think you need to define a tolerance of result. This will be an absolute value I think.

Yes some tolerance will be defined. But in anyway if there are no some facilities from Simulink/Sysgen to define precision properties of processings block, it will be very boring to define them manually, moreover uncarefull settings would involve overflow errors or hardware overuse.

Regards.

Pavel.

Participant
7,370 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

Continuing to develop processing function I've got an intermediate value -1.003241195100090e+019. For such values even Full precision isn't sufficient. In order to simulation run, I must change Implementation setting of concerned block to Use behavioral HDL (instead of Fabric). Does that mean, that synthesis of such function will fail ?

Regards,

Pavel.

Xilinx Employee
7,360 Views
Registered: ‎08-02-2011

## Re: Floating Point processing strategy

It would be nice to see your signal dimensions (Format -> Port/Signal Displays -> Signal Dimensions).

FYI, SysGen floating point blocks support single, double, or custom precision floats.

@pavel47 wrote:

In order to simulation run, I must change Implementation setting of concerned block to Use behavioral HDL (instead of Fabric). Does that mean, that synthesis of such function will fail ?

In general, no this only means that you're generating Behavioral HDL instead of using CoreGen on the backend. However, with Floating Point blocks behavioral HDL won't be generated. The core will still be used behind the scenes, so it will synthesize fine.

www.xilinx.com
Participant
7,352 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

Hello Bwiec,

Thanks for response. Unfortunately signal dimensions didn't appear. Maybe for Xilinx block this option doesn't work.

In the maintime, continuing to complete the model (I started with reduced version) I've met unavoidable problem. In the processing function there are irrational (sqrt) and trigonometric (sin, cos, atan) functions that enter on the scene. For these function I try to use CORDIC 4.0. It merely doesn't work because the size of the input signal is 134bit (this signal comes from some Xilinx block with Output Precision = Full). Here is error message that appears when simulation fails:

Input_Width: Value '134' is out of range '[8..48]'.

I remain perplexed concerning the possibility to resolve the problem using only Xilinx core blocks of type Multiplier, AddSub.

Is there some other approach, that better matches my case ?

Regards.

Pavel.

P.S. For those, who want to make the acquaintance of problem, I put my model in attachement. Thanks in advance.

Xilinx Employee
7,346 Views
Registered: ‎08-02-2011

## Re: Floating Point processing strategy

After selecting to display signal dimenstions, press ctl+d to update the diagram with the values. They may not show up if you have other sysgen errors.

I also wanted to make sure that you understand that 'Full Precision' only means that a block does not truncate the output. This does not necessarily tell you how wide the output is.

Also, if I recall correctly, our CORDIC core only allows a max of 48 bits of precision on the inputs.

www.xilinx.com
Participant
7,340 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

@bwiec wrote:

After selecting to display signal dimenstions, press ctl+d to update the diagram with the values. They may not show up if you have other sysgen errors.

Ctrl+D doesn't affect appearance (simulation run without errors). Resimulation with Show signal dimensions set also has no effect.

bwiec wrote:

Also, if I recall correctly, our CORDIC core only allows a max of 48 bits of precision on the inputs.

Yes, according to error message it's the case. But how to proceed if the size of signal value is more than 48 bits (even if fractional part is supressed, or binary point position = 0) ?

Is there some Xilinx Manual / Application Note that treats calculations with real numbers (with smart control of precision settings for intermediate results).

For example if some intermediate result has a value that imlies its size surpassing some hardware limit (if such limit exists ?), how to proceed in this case ?

Regards,

Pavel.

Xilinx Employee
7,326 Views
Registered: ‎11-28-2007

## Re: Floating Point processing strategy

Starting in IDS 13.3, you can build SysGen models using floating point data types. I modified your model to take floating point inputs and below is what it looks like when Format->Port/Signal Displays->Port Data Types is turned on. Note that the data types inside SysGen now is xFloat_8_24 or single precision floating point. The modified model is attached in the attachment area. Please give it a try and see if it works better for you.

Cheers,
Jim
Participant
7,282 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

Hello Jim,

Thank you for response. In my library there is no blocks that correspond to your SquareRoot (please, see the picture).

Regards,

Pavel.

Xilinx Employee
6,009 Views
Registered: ‎08-02-2011

## Re: Floating Point processing strategy

That's generally because you aren't running a SysGen version that has that block/IP.

www.xilinx.com
Participant
6,007 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

The mine is 13.2
Xilinx Employee
6,006 Views
Registered: ‎08-02-2011

## Re: Floating Point processing strategy

@pavel47 wrote:
The mine is 13.2

13.2 doesn't support the floating point blocks (most of the new ones anyway). Those were introduced in 13.3

www.xilinx.com
Participant
6,002 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

The LogiCORE IP Floating-Point Operator (FPO) v5.0 Product Specification (DS335 March 1, 2011) assert that FPO v5.0 is supported since 13.1.

Xilinx Employee
7,056 Views
Registered: ‎08-02-2011

## Re: Floating Point processing strategy

True that the FPO core was supported. But the SysGen FP blocks didn't exist previously. Look in your library browser... is there a Floating Point blockset in SysGen, similar to my 13.3 install shown here

www.xilinx.com
Participant
5,996 Views
Registered: ‎10-31-2011

## Re: Floating Point processing strategy

No in my version there is no Floating Point group. :smileysad:

Xilinx Employee
5,994 Views
Registered: ‎08-02-2011