UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie doug1963
Newbie
5,686 Views
Registered: ‎02-16-2016

Half-band filter center tap

Hi,

 

I'm designing a half-band decimate by 2 filter using the FIR compiler.  The filter operates with 16 clock cycles per output sample.  The filter has 63 taps so consequently there are 16 unique coefficients when taking into account symmetry and zero coefficients.  The center coefficient of any halfband filter is equal to 0.5 and should not require the use of a DSP slice as this is nothing by a data shift.  When I put the information into the FIR compiler it indicates that 2 DSP slices are required.  I think it should only require 1 slice.  It seems that the FIR compiler does not exploit the trivial center tap.  Is this the case?

 

Thanks

-Doug

0 Kudos