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Did you mean: talitha
Observer
20,176 Views
Registered: ‎12-06-2007

## How to calculate the RMS within an FPGA/system generator

Hi,

Has anyone experience with the calculation of the RMS of a signal within the FPGA, or more precise how to build this with System Generator.

I have seen a CORDIC sqrt block, that can calculate the square root of a signal, but now it is necessary to calculate the square root of the sum of squared signals.

sqrt ((x1^2 + x2^2+ x3^3+xn^n) / n  )

T
9 Replies Instructor
20,167 Views
Registered: ‎08-14-2007

## Re: How to calculate the RMS within an FPGA/system generator

I think you meant:

sqrt ((x1^2 + x2^2+ x3^2+xn^2) / n  )

or

sqrt ((x1*x1 + x2*x2 + x3*x3 ... + xn*xn) / n)

Squaring a signal is just multiplying by itself.
If you are oprating on successive samples of a single input, you can use a multiply-accumulate function to square and add the samples.  Then every nth sample you multiply the sum by 1/n (easier if n is a power of 2) and reset the accumulator for the next n samples.  If n is not constant, for example if you want to do the sum over one cycle of an input waveform and you don't know the frequency beforehand, you'll need to do the division in the FPGA as well, however remember that you have n clock cycles to do the division before the next sum arrives.

HTH,
Gabor
-- Gabor talitha
Observer
20,070 Views
Registered: ‎12-06-2007

## Re: How to calculate the RMS within an FPGA/system generator

How can I than calculate the RMS when I have an I and a Q path?

Since you than first needs to take the square root of the I and Q related samples. And using a Cordic Sqrt is only possible for Unsigned signals, and I am currently using a signed signal.

sqrt(I1^2+Q1^2)

Talitha Instructor
20,067 Views
Registered: ‎08-14-2007

## Re: How to calculate the RMS within an FPGA/system generator

While I and Q may be signed, I squared plus Q squared will always be positive and thus can be represented as an unsigned value for the Cordic routine.
-- Gabor 18,765 Views
Registered: ‎08-20-2007

## Re:

Hallo.

This is my schematic, which calculates RMS of my voltage signals. It works fine.

The input signals with sampling rate 50Mhz are downsampled and powered ^2 with one multiplier.

Then they downsampled in that way to receive 128 samples per one 50Hz Period.

Those samples are accumulated, shifted to the right by 7 bits  and passed to sqrt unit. I made my own sqrt, because cordic used a lot of recources with my data width. Input signals were Fix16, Accumulator has 39bits(16+16+7). SQRT has 32 bits input and 16 bit output.

SQRT worked by easy formula:

max=x;
min=0;

loop 128 times
{
mid=(max+min)/2;
mid_2=mid*mid;
if (mid_2 > x) max=mid;
else min=mid;
}
return min;

Note: I used TDM because I need a lot of measurements and made them only with one multiplier and sqrt.

Message Edited by syoma on 05-27-2008 09:46 AM abraren
Visitor
11,279 Views
Registered: ‎10-19-2011

## Re:

the inputs In1, In2, In3, of first block....? that should be connected. eilert
11,267 Views
Registered: ‎08-14-2007

## Re: Re:

Hi,

connected to what , and why?

These are input terminator blocks, and everything is fine that way.

They can be fed from a higher hierarchy or from some matlab script.

Very good design practice.

Have a nice simulation

Eilert abraren
Visitor
11,268 Views
Registered: ‎10-19-2011

## Re: Re:

hello
for example I calculate the rms value of 120 Vpp signal at 60 Hz, I get from a source of SimPowerSystems. I should sample the signal first and then connect to the inputs, but do not understand which of the entries you have (In1, In2, In3), on the other side to calculate the square root of the signal block seems to be somewhat incomplete.
Why not try to convert the block of "Discrete rms value" of SimPowerSystems Xilinx Blockset blocks of ..?
I tried this but I have problems in integrating the signal, but it seems a less complicated method.

best regards eilert
11,253 Views
Registered: ‎08-14-2007

## Re: Re:

Hi,

SimPowerSystems is a Simulink extension for simulation of (well...) power systems.

System Generator for DSP is for Hardware simulation AND synthesis of Xilinx FPGAs.

The solution for RMS calculation shown by syoma is application specific and capable of calculationg RMS values for three independent channels with minimal hardware effort (only one multiplier and one sqrt block) and it is probably expandable to 5 channels without sweat, thanks to the Time Division Multiplexers. Very clever design.

The RMS value of In1 can be read from the Register UL1 and so on for In2 and In3.

Of course the RMS calculation consumes some time, therefore one has to wait some time for the correct value to appear in the register.

Even if you may succeed in the creation of a one channel RMS block, similar to the mentioned thing from the SimPowerSystems blockset, compared to syomas solution you would waste ressources of the FPGA if you were going to implement a multi channel application.

Also, what's so complicated about doing an integration of some signal.

You use an Accumulating Register to sum up some samples (Preferably a 2^N number) and simply divide them by shifting the result down for N bits, which costs no hardware at all.

Besides, when you have an application in mind that should deal with 120Vpp on the input, it might be a good idea to spend some thoughts on how to adapt the signal to the FPGA. It won't be a good idea to put an FPGA directly into a wall plug. (Just kiddding, I know you wouldn't do that. ;-) )

Have a nice synthesis

Eilert Explorer
11,079 Views
Registered: ‎02-28-2011

## Re: Re:

pls find attched another aproach to calculate the RMS value. (128 points per period).

The cross input must be high for 1 system clock once a new input period starts (design was meant to work around 30-70Hz input). All inputs and outputs are at system rate

Right now it calculates the RMS value from each of 9 FIX_16_0 inputs in time domain multiplexing and an even less ressource using way then above (if used with more than 3 channels). It can easily be increased to 32 channels by changing the input down sampling blocks to 2*number of channels and the output up sampling to 256*number of channels. Only other blocks to change (besides the time domain blocks) are all the blocks with names inside the RMS Control block

The design is more complicated then the example above but saves adders and memory of the accumulators. In addition it works with different input frequencies. I recommend to start with the example above and if you need more channels and ressource savings then switch to this one. 