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Visitor mubahceci
Visitor
245 Views
Registered: ‎11-05-2018

Questions about FIR Compiler Reload and Config, and Changing output values

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Hi everyone,

In our project, we want to use FIR compiler with reloadable coefficients., but I have questions about it.

First of all, can I clear a reload slot(I mean that can I clear loaded coefficients for a reload slot?) I want to design a project that I can create or change coefficients in a block ram, and gives to reload channel of FIR to change the reload packet already loaded to FIR compiler. I tried to use aresetn, but I guess it just changes data port of the FIR.

Second, I read the manual many times, but I do not understand something about config channel. For each relaod packet(fir filter coefficient packet), as far as I understand that I need to send config tlast and config tdata for each reload packet, right?

And final question is about changing of amplitude of the output. My coefficients and inputs are 16-bits, and I have 128 coefficients, which means that total output for each input sample is 39-bit. However, I want to take 16-bits rather than full-precision of FIR compiler. In this situation, I could not decide to take which part of the 39-bit as my output. If I think a lowpass filter, in the passband, my outputs cannot be decreased a lot. Also, I think that 15 bit of a coefficient actually is fractional part of  the coefficient, and I used fixed point representation for them. Hence, I think that I need to take [31:15] part of the full-precision, since first 15 bits LSB of the full-precision is related to fractional part. Does it also correct?

Thanks in advance.

Sincerely,

Umut

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Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎09-18-2018

Re: Questions about FIR Compiler Reload and Config, and Changing output values

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Hi @mubahceci ,

First it is possible to reload a new set of coefficients into the FIR core by applying the new coeff on the Reload channel tdata bus.

Once the reload channel coefficients are applied to the core, the reload slots are free to be loaded into the FIR core again. Please note the reload coeff slots are limited to number of coeffcients the Filter was originally designed with.

Resetting will not clear the already loaded coeffs.

The config channel acts as a synchronization event for the reload procedure. The config channel tdata indicates the FIR core to take in the data. Please see the PG reload filer coeff sections that describe this. Thus valid config tdata is necessary for loading in the Reloadable coeff.

Reg 3rd point, the FIR compiler's implementation tab provides the facility to enter the fractional bits for coeffs, input and shows the number of fractional bits on output. You might want to use this information for selection of the decreased precision option.

If using a system generator design, there are converter blocks to change from one precision to another.

 

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Xilinx Employee
Xilinx Employee
190 Views
Registered: ‎09-18-2018

Re: Questions about FIR Compiler Reload and Config, and Changing output values

Jump to solution

Hi @mubahceci ,

First it is possible to reload a new set of coefficients into the FIR core by applying the new coeff on the Reload channel tdata bus.

Once the reload channel coefficients are applied to the core, the reload slots are free to be loaded into the FIR core again. Please note the reload coeff slots are limited to number of coeffcients the Filter was originally designed with.

Resetting will not clear the already loaded coeffs.

The config channel acts as a synchronization event for the reload procedure. The config channel tdata indicates the FIR core to take in the data. Please see the PG reload filer coeff sections that describe this. Thus valid config tdata is necessary for loading in the Reloadable coeff.

Reg 3rd point, the FIR compiler's implementation tab provides the facility to enter the fractional bits for coeffs, input and shows the number of fractional bits on output. You might want to use this information for selection of the decreased precision option.

If using a system generator design, there are converter blocks to change from one precision to another.

 

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