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3,050 Views
Registered: ‎07-28-2011

Regarding integrating two ip cores.. FFT and FIR

Hi,

 

I  am using system generator.

I want to design a system, in which a signal passes through a FIR filter and then , later through a FFT.

 

 

 

I used a FIR 6.0 and FFT 7.1

 

after passing through FIR, the 14 bit input which i gave is turned into a 34 bit output from FIR. I think this may be due to the filter coeffiecients.

 

Later, i converted this into 14 bit (13 bit fractioanl part) and i gave this as an input to the FFT.

 

I built this and i created verilog code and i instantiated in a proper way and i dumped it into FPGA (VIRTEX-4) .

 

I am able to see the proper output at the simulation (scope), but i am unable to produce the same output through FPGA.

 

 i am observing output using chipscope.

 

I am getting many peaks at the FFT output, where only one high peak need to observed.

 

My sampling frequency is 50MHz, input is 5 Mhz, (i am doing Band pass filtering 4.5-5.5 Mhz)

I need to get a perfect output through FPGA,  but i am not getting it.

 

Can you please help me, what might went wrong?

 

 

Because, when i use a single FFT, i am geeting a proper output, but, when i use both FFT and FIR combinely, i am facing this problem.

 

 

 

 

 

 

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2 Replies
Xilinx Employee
Xilinx Employee
3,045 Views
Registered: ‎08-02-2011

Re: Regarding integrating two ip cores.. FFT and FIR

Hello,

 

Is it possible for you to post some data? Chipscope plots showing the behavior?

 

Also, so you're aware, you will have some error coming from 34-bit -> 14-bit truncation. You may want to let the FIR compiler do some rounding for you before output truncation (or do the rounding yourself).

 

You should also be aware that you will likely see windowing effects of the FFT as well (which will manifest themselves in the manner which you had described)

www.xilinx.com
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Xilinx Employee
Xilinx Employee
3,026 Views
Registered: ‎08-01-2007

Re: Regarding integrating two ip cores.. FFT and FIR

In addition you might want to use the FFT v8.0 with the FIR Compiler v6.0 and later.  This will be useful because both support AXI.

 

You are correct that you will see bit growth comming out of the FIR Compiler, but you can reduce the output width in the FIR Compiler GUI.

Chris
Video Design Hub | Embedded SW Support

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