UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
5,967 Views
Registered: ‎10-31-2010

Unable to see System Generator Clock from Blackbox

Hello,one interesting question i came across by one of my friends Luis Manuel that , how can we see the clock of system generator?

 

I have written one verilog code, in which:

 

Initialization of d as d=0, then doing d=~d at every positive edge of clk.

clk_out=clk has been assigned.

 

module firs(clk,ce,clk_out,d);
input clk,ce;
output clk_out;
output reg d;

assign clk_out=clk;
initial
begin
d=0;
end


always @(posedge clk)
begin
d=~d;
end
endmodule

 

 

model.png

 

After running the program, in Wavescope i get is,

 

model.png

 

Clk_out is always remaining 0.

 

So always@(posedge clk) whatever operation was there =>Invert d that took place, but we are not able to see the clk.

 

Regards,

Vihang Naik
0 Kudos
5 Replies
Voyager
Voyager
5,964 Views
Registered: ‎05-09-2008

Re: Unable to see System Generator Clock from Blackbox

Hi,

 

Why you want a clock of the black box ?

 

If you want use a clock of model use "Clock Probe" on "Xilinx Blockset -> Tools"

 

secureasm

0 Kudos
Contributor
Contributor
5,962 Views
Registered: ‎10-31-2010

Re: Unable to see System Generator Clock from Blackbox

Hello,thanks for your reply.

Yes,I totally agree that Clock Probe gives us clock, .

But without using it as i have written the program, logically it should work,why it is remaining 0 all the time.

In the same program,one operation is done with respect to clk,so why we are not able to see the same?
Vihang Naik
0 Kudos
Xilinx Employee
Xilinx Employee
5,953 Views
Registered: ‎10-12-2011

Re: Unable to see System Generator Clock from Blackbox

Hi,

 

you are trying to see two signals from the Simulink domain (after gateway out) in Wavescope that is used to plot signals from System Generator, are you sure this is allowed?

 

0 Kudos
Scholar joelby
Scholar
5,947 Views
Registered: ‎10-05-2010

Re: Unable to see System Generator Clock from Blackbox

I'm not 100% sure I understand your problem because it involves System Generator, but I imagine it is because you're trying to sample clk_out using clk as the sampling clock. If you sample a signal using that signal as a trigger, the value will be constant and either zero or one depending on the clock edge you're sampling on (disregarding setup/hold times, etc.)

 

As an analogy, imagine trying to take a photograph of a camera in a mirror. From viewing a series of photos, you might think that the camera's shutter is always open, but this is just because of your sampling method. You'd need to sample the clock signal at both edges of the clock (or somehow take a photograph of the camera when the shutter is closed), or use a different, faster clock.

 

Contributor
Contributor
5,945 Views
Registered: ‎10-31-2010

Re: Unable to see System Generator Clock from Blackbox

Hello edelcas,

As far as i know it allows,otherwise if it did not allow then we would not have been able to see the second signal in wavescope(see screenshot above).
Vihang Naik
0 Kudos